Architecture for implementing an integrated capacitance

An architecture for implementing an integrated capacity includes a capacitive block inserted between first and second voltage references. The block is formed from elementary capacitive modules. An enable block is inserted between the first voltage reference and the capacitive block and includes swit...

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Bibliographische Detailangaben
Hauptverfasser: PISASALE MICHELANGELO, SAMBATARO VINCENZO, GAIBOTTI MAURIZIO, LA PLACA MICHELE
Format: Patent
Sprache:eng
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Zusammenfassung:An architecture for implementing an integrated capacity includes a capacitive block inserted between first and second voltage references. The block is formed from elementary capacitive modules. An enable block is inserted between the first voltage reference and the capacitive block and includes switches connected to the elementary capacitive modules and driven on their control terminals by control signals. Each switch of the enable block is inserted between the first voltage reference and a first end of a corresponding elementary capacitive module. A verify and enable circuit is connected to the first voltage reference, as well as at the input of the first end of the elementary capacitive modules and at the output of the control terminals of the switches of the enable block. The verify and enable circuit detects the presence of a current value in each of the elementary capacitive modules and, if said current is detected, disables that elementary capacitive module of the capacitive block using the corresponding switch of the enable block.