Loop manipulation in a behavioral synthesis tool
Methods and apparatus for analyzing and processing loops within an integrated circuit design are described. According to one embodiment, the processing comprises unrolling loops. In another embodiment, the processing comprises pipelining loops. In yet another embodiment, the processing comprises mer...
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| creator | BOWYER BRYAN DARRELL GUTBERLET PETER PIUS TAKACH ANDRES R |
| description | Methods and apparatus for analyzing and processing loops within an integrated circuit design are described. According to one embodiment, the processing comprises unrolling loops. In another embodiment, the processing comprises pipelining loops. In yet another embodiment, the processing comprises merging loops. In any of the disclosed embodiments, loops comprise independent loops, dependent loops or some combination thereof. Other embodiments for processing loops are disclosed, as well as integrated circuits and circuit design databases resulting from the disclosed methods. Computer-executable media storing instructions for performing the disclosed methods are also disclosed. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7412684B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7412684B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7412684B23</originalsourceid><addsrcrecordid>eNrjZDDwyc8vUMhNzMssKM1JLMnMz1PIzFNIVEhKzUgsy8wvSsxRKK7MK8lILc4sVijJz8_hYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxocHmJoZGZhYmTkbGRCgBACabK1E</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Loop manipulation in a behavioral synthesis tool</title><source>esp@cenet</source><creator>BOWYER BRYAN DARRELL ; GUTBERLET PETER PIUS ; TAKACH ANDRES R</creator><creatorcontrib>BOWYER BRYAN DARRELL ; GUTBERLET PETER PIUS ; TAKACH ANDRES R</creatorcontrib><description>Methods and apparatus for analyzing and processing loops within an integrated circuit design are described. According to one embodiment, the processing comprises unrolling loops. In another embodiment, the processing comprises pipelining loops. In yet another embodiment, the processing comprises merging loops. In any of the disclosed embodiments, loops comprise independent loops, dependent loops or some combination thereof. Other embodiments for processing loops are disclosed, as well as integrated circuits and circuit design databases resulting from the disclosed methods. Computer-executable media storing instructions for performing the disclosed methods are also disclosed.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080812&DB=EPODOC&CC=US&NR=7412684B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080812&DB=EPODOC&CC=US&NR=7412684B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BOWYER BRYAN DARRELL</creatorcontrib><creatorcontrib>GUTBERLET PETER PIUS</creatorcontrib><creatorcontrib>TAKACH ANDRES R</creatorcontrib><title>Loop manipulation in a behavioral synthesis tool</title><description>Methods and apparatus for analyzing and processing loops within an integrated circuit design are described. According to one embodiment, the processing comprises unrolling loops. In another embodiment, the processing comprises pipelining loops. In yet another embodiment, the processing comprises merging loops. In any of the disclosed embodiments, loops comprise independent loops, dependent loops or some combination thereof. Other embodiments for processing loops are disclosed, as well as integrated circuits and circuit design databases resulting from the disclosed methods. Computer-executable media storing instructions for performing the disclosed methods are also disclosed.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDwyc8vUMhNzMssKM1JLMnMz1PIzFNIVEhKzUgsy8wvSsxRKK7MK8lILc4sVijJz8_hYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxocHmJoZGZhYmTkbGRCgBACabK1E</recordid><startdate>20080812</startdate><enddate>20080812</enddate><creator>BOWYER BRYAN DARRELL</creator><creator>GUTBERLET PETER PIUS</creator><creator>TAKACH ANDRES R</creator><scope>EVB</scope></search><sort><creationdate>20080812</creationdate><title>Loop manipulation in a behavioral synthesis tool</title><author>BOWYER BRYAN DARRELL ; GUTBERLET PETER PIUS ; TAKACH ANDRES R</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7412684B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>BOWYER BRYAN DARRELL</creatorcontrib><creatorcontrib>GUTBERLET PETER PIUS</creatorcontrib><creatorcontrib>TAKACH ANDRES R</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BOWYER BRYAN DARRELL</au><au>GUTBERLET PETER PIUS</au><au>TAKACH ANDRES R</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Loop manipulation in a behavioral synthesis tool</title><date>2008-08-12</date><risdate>2008</risdate><abstract>Methods and apparatus for analyzing and processing loops within an integrated circuit design are described. According to one embodiment, the processing comprises unrolling loops. In another embodiment, the processing comprises pipelining loops. In yet another embodiment, the processing comprises merging loops. In any of the disclosed embodiments, loops comprise independent loops, dependent loops or some combination thereof. Other embodiments for processing loops are disclosed, as well as integrated circuits and circuit design databases resulting from the disclosed methods. Computer-executable media storing instructions for performing the disclosed methods are also disclosed.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Loop manipulation in a behavioral synthesis tool |
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