Process for fabricating a semiconductor package and semiconductor package with leadframe

A semiconductor package includes a flat metal leadframe including spaced apart portions, at least some of which constitute electrical connection leads. A filling material fills the spaces that separate the spaced apart portions of the leadframe to form a plate before fastening an integrated circuit...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: TEYSSEYRE JEROME, DIOT JEAN-LUC
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator TEYSSEYRE JEROME
DIOT JEAN-LUC
description A semiconductor package includes a flat metal leadframe including spaced apart portions, at least some of which constitute electrical connection leads. A filling material fills the spaces that separate the spaced apart portions of the leadframe to form a plate before fastening an integrated circuit chip to the front of the leadframe. Electrical connections are made between the chip and the electrical connection leads. The chip is then encapsulated on the front of the leadframe using a formed or attached encapsulant.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7358598B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7358598B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7358598B23</originalsourceid><addsrcrecordid>eNrjZIgIKMpPTi0uVkjLL1JIS0wqykxOLMnMS1dIVChOzc1Mzs9LKU0uAcoVJCZnJ6anKiTmpeCQKc8syVDISU1MSStKzE3lYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxUBNqXmpJfGhwebGphamlhZORsZEKAEAY-w6kg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Process for fabricating a semiconductor package and semiconductor package with leadframe</title><source>esp@cenet</source><creator>TEYSSEYRE JEROME ; DIOT JEAN-LUC</creator><creatorcontrib>TEYSSEYRE JEROME ; DIOT JEAN-LUC</creatorcontrib><description>A semiconductor package includes a flat metal leadframe including spaced apart portions, at least some of which constitute electrical connection leads. A filling material fills the spaces that separate the spaced apart portions of the leadframe to form a plate before fastening an integrated circuit chip to the front of the leadframe. Electrical connections are made between the chip and the electrical connection leads. The chip is then encapsulated on the front of the leadframe using a formed or attached encapsulant.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080415&amp;DB=EPODOC&amp;CC=US&amp;NR=7358598B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080415&amp;DB=EPODOC&amp;CC=US&amp;NR=7358598B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TEYSSEYRE JEROME</creatorcontrib><creatorcontrib>DIOT JEAN-LUC</creatorcontrib><title>Process for fabricating a semiconductor package and semiconductor package with leadframe</title><description>A semiconductor package includes a flat metal leadframe including spaced apart portions, at least some of which constitute electrical connection leads. A filling material fills the spaces that separate the spaced apart portions of the leadframe to form a plate before fastening an integrated circuit chip to the front of the leadframe. Electrical connections are made between the chip and the electrical connection leads. The chip is then encapsulated on the front of the leadframe using a formed or attached encapsulant.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZIgIKMpPTi0uVkjLL1JIS0wqykxOLMnMS1dIVChOzc1Mzs9LKU0uAcoVJCZnJ6anKiTmpeCQKc8syVDISU1MSStKzE3lYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxUBNqXmpJfGhwebGphamlhZORsZEKAEAY-w6kg</recordid><startdate>20080415</startdate><enddate>20080415</enddate><creator>TEYSSEYRE JEROME</creator><creator>DIOT JEAN-LUC</creator><scope>EVB</scope></search><sort><creationdate>20080415</creationdate><title>Process for fabricating a semiconductor package and semiconductor package with leadframe</title><author>TEYSSEYRE JEROME ; DIOT JEAN-LUC</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7358598B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>TEYSSEYRE JEROME</creatorcontrib><creatorcontrib>DIOT JEAN-LUC</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TEYSSEYRE JEROME</au><au>DIOT JEAN-LUC</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Process for fabricating a semiconductor package and semiconductor package with leadframe</title><date>2008-04-15</date><risdate>2008</risdate><abstract>A semiconductor package includes a flat metal leadframe including spaced apart portions, at least some of which constitute electrical connection leads. A filling material fills the spaces that separate the spaced apart portions of the leadframe to form a plate before fastening an integrated circuit chip to the front of the leadframe. Electrical connections are made between the chip and the electrical connection leads. The chip is then encapsulated on the front of the leadframe using a formed or attached encapsulant.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US7358598B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Process for fabricating a semiconductor package and semiconductor package with leadframe
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-15T13%3A30%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TEYSSEYRE%20JEROME&rft.date=2008-04-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7358598B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true