Electronic package with optimized lamination process

An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperatur...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: FARQUHAR DONALD S, KLODOWSKI MICHAEL J, HERARD JAMES D, QUESTAD DAVID, WOAN DER-JIN
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator FARQUHAR DONALD S
KLODOWSKI MICHAEL J
HERARD JAMES D
QUESTAD DAVID
WOAN DER-JIN
description An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7329816B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7329816B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7329816B23</originalsourceid><addsrcrecordid>eNrjZDBxzUlNLinKz8tMVihITM5OTE9VKM8syVDILyjJzM2sSk1RyEnMzcxLLMnMz1MoKMpPTi0u5mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcVAc1LzUkviQ4PNjY0sLQzNnIyMiVACABb6LSU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Electronic package with optimized lamination process</title><source>esp@cenet</source><creator>FARQUHAR DONALD S ; KLODOWSKI MICHAEL J ; HERARD JAMES D ; QUESTAD DAVID ; WOAN DER-JIN</creator><creatorcontrib>FARQUHAR DONALD S ; KLODOWSKI MICHAEL J ; HERARD JAMES D ; QUESTAD DAVID ; WOAN DER-JIN</creatorcontrib><description>An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080212&amp;DB=EPODOC&amp;CC=US&amp;NR=7329816B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080212&amp;DB=EPODOC&amp;CC=US&amp;NR=7329816B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FARQUHAR DONALD S</creatorcontrib><creatorcontrib>KLODOWSKI MICHAEL J</creatorcontrib><creatorcontrib>HERARD JAMES D</creatorcontrib><creatorcontrib>QUESTAD DAVID</creatorcontrib><creatorcontrib>WOAN DER-JIN</creatorcontrib><title>Electronic package with optimized lamination process</title><description>An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDBxzUlNLinKz8tMVihITM5OTE9VKM8syVDILyjJzM2sSk1RyEnMzcxLLMnMz1MoKMpPTi0u5mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcVAc1LzUkviQ4PNjY0sLQzNnIyMiVACABb6LSU</recordid><startdate>20080212</startdate><enddate>20080212</enddate><creator>FARQUHAR DONALD S</creator><creator>KLODOWSKI MICHAEL J</creator><creator>HERARD JAMES D</creator><creator>QUESTAD DAVID</creator><creator>WOAN DER-JIN</creator><scope>EVB</scope></search><sort><creationdate>20080212</creationdate><title>Electronic package with optimized lamination process</title><author>FARQUHAR DONALD S ; KLODOWSKI MICHAEL J ; HERARD JAMES D ; QUESTAD DAVID ; WOAN DER-JIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7329816B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>FARQUHAR DONALD S</creatorcontrib><creatorcontrib>KLODOWSKI MICHAEL J</creatorcontrib><creatorcontrib>HERARD JAMES D</creatorcontrib><creatorcontrib>QUESTAD DAVID</creatorcontrib><creatorcontrib>WOAN DER-JIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FARQUHAR DONALD S</au><au>KLODOWSKI MICHAEL J</au><au>HERARD JAMES D</au><au>QUESTAD DAVID</au><au>WOAN DER-JIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Electronic package with optimized lamination process</title><date>2008-02-12</date><risdate>2008</risdate><abstract>An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US7329816B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
SEMICONDUCTOR DEVICES
title Electronic package with optimized lamination process
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-21T18%3A30%3A48IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=FARQUHAR%20DONALD%20S&rft.date=2008-02-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7329816B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true