Selective plating of package terminals
In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a seco...
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| creator | WOOD DUSTIN P MALLIK DEBENDRA |
| description | In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7321172B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7321172B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7321172B23</originalsourceid><addsrcrecordid>eNrjZFALTs1JTS7JLEtVKMhJLMnMS1fIT1MoSEzOTkxPVShJLcrNzEvMKeZhYE0DUqm8UJqbQcHNNcTZQze1ID8-tRioPjUvtSQ-NNjc2MjQ0NzIyciYCCUAKlInUA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Selective plating of package terminals</title><source>esp@cenet</source><creator>WOOD DUSTIN P ; MALLIK DEBENDRA</creator><creatorcontrib>WOOD DUSTIN P ; MALLIK DEBENDRA</creatorcontrib><description>In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080122&DB=EPODOC&CC=US&NR=7321172B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080122&DB=EPODOC&CC=US&NR=7321172B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WOOD DUSTIN P</creatorcontrib><creatorcontrib>MALLIK DEBENDRA</creatorcontrib><title>Selective plating of package terminals</title><description>In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFALTs1JTS7JLEtVKMhJLMnMS1fIT1MoSEzOTkxPVShJLcrNzEvMKeZhYE0DUqm8UJqbQcHNNcTZQze1ID8-tRioPjUvtSQ-NNjc2MjQ0NzIyciYCCUAKlInUA</recordid><startdate>20080122</startdate><enddate>20080122</enddate><creator>WOOD DUSTIN P</creator><creator>MALLIK DEBENDRA</creator><scope>EVB</scope></search><sort><creationdate>20080122</creationdate><title>Selective plating of package terminals</title><author>WOOD DUSTIN P ; MALLIK DEBENDRA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7321172B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>WOOD DUSTIN P</creatorcontrib><creatorcontrib>MALLIK DEBENDRA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WOOD DUSTIN P</au><au>MALLIK DEBENDRA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Selective plating of package terminals</title><date>2008-01-22</date><risdate>2008</risdate><abstract>In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
| title | Selective plating of package terminals |
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