Network processor architecture
A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and d...
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creator | CHEN STEVE C CHIANG TONY J LEE BARRY T GERSHMAN CHARLES F YANG ERIC K CHONG SIMON S BLESZYNSKI RYZSARD ONO GOICHIRO TRINH MAN D TSONG JUN-WEN |
description | A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service ("QoS"). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7310348B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7310348B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7310348B23</originalsourceid><addsrcrecordid>eNrjZJDzSy0pzy_KVigoyk9OLS7OL1JILErOyCxJTS4pLUrlYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxocHmxoYGxiYWTkbGRCgBAPF3JNg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Network processor architecture</title><source>esp@cenet</source><creator>CHEN STEVE C ; CHIANG TONY J ; LEE BARRY T ; GERSHMAN CHARLES F ; YANG ERIC K ; CHONG SIMON S ; BLESZYNSKI RYZSARD ; ONO GOICHIRO ; TRINH MAN D ; TSONG JUN-WEN</creator><creatorcontrib>CHEN STEVE C ; CHIANG TONY J ; LEE BARRY T ; GERSHMAN CHARLES F ; YANG ERIC K ; CHONG SIMON S ; BLESZYNSKI RYZSARD ; ONO GOICHIRO ; TRINH MAN D ; TSONG JUN-WEN</creatorcontrib><description>A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service ("QoS"). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071218&DB=EPODOC&CC=US&NR=7310348B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071218&DB=EPODOC&CC=US&NR=7310348B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHEN STEVE C</creatorcontrib><creatorcontrib>CHIANG TONY J</creatorcontrib><creatorcontrib>LEE BARRY T</creatorcontrib><creatorcontrib>GERSHMAN CHARLES F</creatorcontrib><creatorcontrib>YANG ERIC K</creatorcontrib><creatorcontrib>CHONG SIMON S</creatorcontrib><creatorcontrib>BLESZYNSKI RYZSARD</creatorcontrib><creatorcontrib>ONO GOICHIRO</creatorcontrib><creatorcontrib>TRINH MAN D</creatorcontrib><creatorcontrib>TSONG JUN-WEN</creatorcontrib><title>Network processor architecture</title><description>A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service ("QoS"). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJDzSy0pzy_KVigoyk9OLS7OL1JILErOyCxJTS4pLUrlYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxocHmxoYGxiYWTkbGRCgBAPF3JNg</recordid><startdate>20071218</startdate><enddate>20071218</enddate><creator>CHEN STEVE C</creator><creator>CHIANG TONY J</creator><creator>LEE BARRY T</creator><creator>GERSHMAN CHARLES F</creator><creator>YANG ERIC K</creator><creator>CHONG SIMON S</creator><creator>BLESZYNSKI RYZSARD</creator><creator>ONO GOICHIRO</creator><creator>TRINH MAN D</creator><creator>TSONG JUN-WEN</creator><scope>EVB</scope></search><sort><creationdate>20071218</creationdate><title>Network processor architecture</title><author>CHEN STEVE C ; CHIANG TONY J ; LEE BARRY T ; GERSHMAN CHARLES F ; YANG ERIC K ; CHONG SIMON S ; BLESZYNSKI RYZSARD ; ONO GOICHIRO ; TRINH MAN D ; TSONG JUN-WEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7310348B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>CHEN STEVE C</creatorcontrib><creatorcontrib>CHIANG TONY J</creatorcontrib><creatorcontrib>LEE BARRY T</creatorcontrib><creatorcontrib>GERSHMAN CHARLES F</creatorcontrib><creatorcontrib>YANG ERIC K</creatorcontrib><creatorcontrib>CHONG SIMON S</creatorcontrib><creatorcontrib>BLESZYNSKI RYZSARD</creatorcontrib><creatorcontrib>ONO GOICHIRO</creatorcontrib><creatorcontrib>TRINH MAN D</creatorcontrib><creatorcontrib>TSONG JUN-WEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHEN STEVE C</au><au>CHIANG TONY J</au><au>LEE BARRY T</au><au>GERSHMAN CHARLES F</au><au>YANG ERIC K</au><au>CHONG SIMON S</au><au>BLESZYNSKI RYZSARD</au><au>ONO GOICHIRO</au><au>TRINH MAN D</au><au>TSONG JUN-WEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Network processor architecture</title><date>2007-12-18</date><risdate>2007</risdate><abstract>A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service ("QoS"). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
title | Network processor architecture |
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