Method and an apparatus to improve hierarchical design implementation

A method and an apparatus to improve hierarchical design implementation have been disclosed. In one embodiment, the method includes deriving boundary logic of at least one of a plurality of partitions in an integrated circuit (IC) design, marking the boundary logic of the at least one of the plurali...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	LI HUNGUN
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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