Half-good mode for large L2 cache array topology with different latency domains

A cache memory logically partitions a cache array into at least two slices each having a plurality of cache lines, with a given cache line spread across two or more cache ways of contiguous bytes and a given cache way shared between the two cache slices, and if one a cache way is defective that is p...

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Bibliographische Detailangaben

Hauptverfasser:	LIVINGSTON KIRK SAMUEL, GUTHRIE GUY LYNN, STARKE WILLIAM JOHN, FIELDS, JR. JAMES STEPHEN
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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