RFID tag design with circuitry for wafer level testing

Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafe...

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Hauptverfasser:	HARA DENNIS KIYOSHI, GLIDDEN ROBERT M, HYDE JOHN D, KUHN JAY A, OLIVER RONALD A
Format:	Patent
Sprache:	eng
Schlagworte:	MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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creator	HARA DENNIS KIYOSHI GLIDDEN ROBERT M HYDE JOHN D KUHN JAY A OLIVER RONALD A
description	Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7307528B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7307528B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7307528B23</originalsourceid><addsrcrecordid>eNrjZDALcvN0UShJTFdISS3OTM9TKM8syVBIzixKLs0sKapUSMsvUihPTEstUshJLUvNUShJLS7JzEvnYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxocHmxgbmpkYWTkbGRCgBAP4ULNY</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>RFID tag design with circuitry for wafer level testing</title><source>esp@cenet</source><creator>HARA DENNIS KIYOSHI ; GLIDDEN ROBERT M ; HYDE JOHN D ; KUHN JAY A ; OLIVER RONALD A</creator><creatorcontrib>HARA DENNIS KIYOSHI ; GLIDDEN ROBERT M ; HYDE JOHN D ; KUHN JAY A ; OLIVER RONALD A</creatorcontrib><description>Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.</description><language>eng</language><subject>MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071211&DB=EPODOC&CC=US&NR=7307528B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071211&DB=EPODOC&CC=US&NR=7307528B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HARA DENNIS KIYOSHI</creatorcontrib><creatorcontrib>GLIDDEN ROBERT M</creatorcontrib><creatorcontrib>HYDE JOHN D</creatorcontrib><creatorcontrib>KUHN JAY A</creatorcontrib><creatorcontrib>OLIVER RONALD A</creatorcontrib><title>RFID tag design with circuitry for wafer level testing</title><description>Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.</description><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDALcvN0UShJTFdISS3OTM9TKM8syVBIzixKLs0sKapUSMsvUihPTEstUshJLUvNUShJLS7JzEvnYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxocHmxgbmpkYWTkbGRCgBAP4ULNY</recordid><startdate>20071211</startdate><enddate>20071211</enddate><creator>HARA DENNIS KIYOSHI</creator><creator>GLIDDEN ROBERT M</creator><creator>HYDE JOHN D</creator><creator>KUHN JAY A</creator><creator>OLIVER RONALD A</creator><scope>EVB</scope></search><sort><creationdate>20071211</creationdate><title>RFID tag design with circuitry for wafer level testing</title><author>HARA DENNIS KIYOSHI ; GLIDDEN ROBERT M ; HYDE JOHN D ; KUHN JAY A ; OLIVER RONALD A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7307528B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>HARA DENNIS KIYOSHI</creatorcontrib><creatorcontrib>GLIDDEN ROBERT M</creatorcontrib><creatorcontrib>HYDE JOHN D</creatorcontrib><creatorcontrib>KUHN JAY A</creatorcontrib><creatorcontrib>OLIVER RONALD A</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HARA DENNIS KIYOSHI</au><au>GLIDDEN ROBERT M</au><au>HYDE JOHN D</au><au>KUHN JAY A</au><au>OLIVER RONALD A</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>RFID tag design with circuitry for wafer level testing</title><date>2007-12-11</date><risdate>2007</risdate><abstract>Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.</abstract><oa>free_for_read</oa></addata></record>
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subjects	MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
title	RFID tag design with circuitry for wafer level testing
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