Stackable single package and stacked multi-chip assembly

A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate contact pads arranged around a periphery portion of the substrate. A chip mounted on the substrate including contact pads that are electrically connected with the conductive wiring of the substrate, and a ring surrounding edges of the chip are also included. The ring is formed from an electrically insulating material and includes a plurality of openings, each opening adjacent a substrate contact pad to allow for electrical connection to the chip though the substrate contact pad.