Method of fabricating semiconductor side wall fin

Method of fabricating semiconductor side wall fin

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

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Hauptverfasser: NOWAK EDWARD J, DIVAKARUNI RAMA, JONES ERIN C, BALLANTINE ARNE W, ADKISSON JAMES W, AGNELLO PAUL D, RANKIN JED H
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator NOWAK EDWARD J
DIVAKARUNI RAMA
JONES ERIN C
BALLANTINE ARNE W
ADKISSON JAMES W
AGNELLO PAUL D
RANKIN JED H
description A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Method of fabricating semiconductor side wall fin
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