Globally observing load operations prior to fence instruction and post-serialization modes

A system includes a memory unit and a processor where the processor has a load buffer to store a first instruction and a cache controller to block the first instruction from dispatch into the cache controller until load data for load operations prior to the first instruction fetched from the memory...

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Bibliographische Detailangaben

Hauptverfasser:	MARR DEBBIE, HACKING LANCE E
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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