Method and apparatus for a dual substrate package
A semiconductor die having a through via formed therein is disclosed. A first conductive layer is formed on the front side of the die and a second conductive layer is formed on the backside of the die, and coupled with the through via. A first package substrate is electrically coupled with the first...
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| creator | SINGH KULJEET RUMER CHRISTOPHER L |
| description | A semiconductor die having a through via formed therein is disclosed. A first conductive layer is formed on the front side of the die and a second conductive layer is formed on the backside of the die, and coupled with the through via. A first package substrate is electrically coupled with the first conductive layer, and a second package substrate is electrically coupled with the second conductive layer. In another embodiment, a substrate ball electrically couples the first and second package substrates. In a further embodiment, a flip chip bump is attached to the first package substrate. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7247517B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7247517B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7247517B23</originalsourceid><addsrcrecordid>eNrjZDD0TS3JyE9RSMwD4oKCxKLEktJihbT8IoVEhZTSxByF4tKk4hKgaKpCQWJydmJ6Kg8Da1piTnEqL5TmZlBwcw1x9tBNLciPTy0GqkrNSy2JDw02NzIxNzU0dzIyJkIJAB5vKyg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for a dual substrate package</title><source>esp@cenet</source><creator>SINGH KULJEET ; RUMER CHRISTOPHER L</creator><creatorcontrib>SINGH KULJEET ; RUMER CHRISTOPHER L</creatorcontrib><description>A semiconductor die having a through via formed therein is disclosed. A first conductive layer is formed on the front side of the die and a second conductive layer is formed on the backside of the die, and coupled with the through via. A first package substrate is electrically coupled with the first conductive layer, and a second package substrate is electrically coupled with the second conductive layer. In another embodiment, a substrate ball electrically couples the first and second package substrates. In a further embodiment, a flip chip bump is attached to the first package substrate.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070724&DB=EPODOC&CC=US&NR=7247517B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070724&DB=EPODOC&CC=US&NR=7247517B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SINGH KULJEET</creatorcontrib><creatorcontrib>RUMER CHRISTOPHER L</creatorcontrib><title>Method and apparatus for a dual substrate package</title><description>A semiconductor die having a through via formed therein is disclosed. A first conductive layer is formed on the front side of the die and a second conductive layer is formed on the backside of the die, and coupled with the through via. A first package substrate is electrically coupled with the first conductive layer, and a second package substrate is electrically coupled with the second conductive layer. In another embodiment, a substrate ball electrically couples the first and second package substrates. In a further embodiment, a flip chip bump is attached to the first package substrate.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD0TS3JyE9RSMwD4oKCxKLEktJihbT8IoVEhZTSxByF4tKk4hKgaKpCQWJydmJ6Kg8Da1piTnEqL5TmZlBwcw1x9tBNLciPTy0GqkrNSy2JDw02NzIxNzU0dzIyJkIJAB5vKyg</recordid><startdate>20070724</startdate><enddate>20070724</enddate><creator>SINGH KULJEET</creator><creator>RUMER CHRISTOPHER L</creator><scope>EVB</scope></search><sort><creationdate>20070724</creationdate><title>Method and apparatus for a dual substrate package</title><author>SINGH KULJEET ; RUMER CHRISTOPHER L</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7247517B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SINGH KULJEET</creatorcontrib><creatorcontrib>RUMER CHRISTOPHER L</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SINGH KULJEET</au><au>RUMER CHRISTOPHER L</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for a dual substrate package</title><date>2007-07-24</date><risdate>2007</risdate><abstract>A semiconductor die having a through via formed therein is disclosed. A first conductive layer is formed on the front side of the die and a second conductive layer is formed on the backside of the die, and coupled with the through via. A first package substrate is electrically coupled with the first conductive layer, and a second package substrate is electrically coupled with the second conductive layer. In another embodiment, a substrate ball electrically couples the first and second package substrates. In a further embodiment, a flip chip bump is attached to the first package substrate.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Method and apparatus for a dual substrate package |
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