Data buffer-controlled digital clock regenerator

A clock regeneration scheme for a digital communication receiver has a first-in, first-out (FIFO) storage buffer into which received data is clocked in accordance with an input clock signal and a data valid signal. A fixed fractional delay line is coupled to provide respectively different phase dela...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	KLIESNER MATTHEW A, RIVES ERIC M, MESTER TIMOTHY G
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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