Method and an apparatus to reduce duty cycle distortion

Method and an apparatus to reduce duty cycle distortion

A method and an apparatus to reduce duty cycle distortion are described. The apparatus may include a first current-mode logic (CML) circuit block comprising a positive input and a negative input and a second CML circuit block coupled in series to the first CML circuit block. The second CML circuit b...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: STIFF JONATHON C, KWAN KING H
Format: Patent
Sprache:eng
Schlagworte:
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator STIFF JONATHON C
KWAN KING H
description A method and an apparatus to reduce duty cycle distortion are described. The apparatus may include a first current-mode logic (CML) circuit block comprising a positive input and a negative input and a second CML circuit block coupled in series to the first CML circuit block. The second CML circuit block may comprise a positive output, a negative output and a first transistor coupled between the positive input and the positive output. The second transistor may be coupled between the negative input and the negative output of the second CML circuit block.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7170319B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7170319B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7170319B13</originalsourceid><addsrcrecordid>eNrjZDD3TS3JyE9RSMwDYYXEgoLEosSS0mKFknyFotSU0uRUhZTSkkqF5MrkHCAzs7gkv6gkMz-Ph4E1LTGnOJUXSnMzKLi5hjh76KYW5MenFhckJqfmpZbEhwabG5obGBtaOhkaE6EEAGgnLZo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and an apparatus to reduce duty cycle distortion</title><source>esp@cenet</source><creator>STIFF JONATHON C ; KWAN KING H</creator><creatorcontrib>STIFF JONATHON C ; KWAN KING H</creatorcontrib><description>A method and an apparatus to reduce duty cycle distortion are described. The apparatus may include a first current-mode logic (CML) circuit block comprising a positive input and a negative input and a second CML circuit block coupled in series to the first CML circuit block. The second CML circuit block may comprise a positive output, a negative output and a first transistor coupled between the positive input and the positive output. The second transistor may be coupled between the negative input and the negative output of the second CML circuit block.</description><language>eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070130&amp;DB=EPODOC&amp;CC=US&amp;NR=7170319B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070130&amp;DB=EPODOC&amp;CC=US&amp;NR=7170319B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>STIFF JONATHON C</creatorcontrib><creatorcontrib>KWAN KING H</creatorcontrib><title>Method and an apparatus to reduce duty cycle distortion</title><description>A method and an apparatus to reduce duty cycle distortion are described. The apparatus may include a first current-mode logic (CML) circuit block comprising a positive input and a negative input and a second CML circuit block coupled in series to the first CML circuit block. The second CML circuit block may comprise a positive output, a negative output and a first transistor coupled between the positive input and the positive output. The second transistor may be coupled between the negative input and the negative output of the second CML circuit block.</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD3TS3JyE9RSMwDYYXEgoLEosSS0mKFknyFotSU0uRUhZTSkkqF5MrkHCAzs7gkv6gkMz-Ph4E1LTGnOJUXSnMzKLi5hjh76KYW5MenFhckJqfmpZbEhwabG5obGBtaOhkaE6EEAGgnLZo</recordid><startdate>20070130</startdate><enddate>20070130</enddate><creator>STIFF JONATHON C</creator><creator>KWAN KING H</creator><scope>EVB</scope></search><sort><creationdate>20070130</creationdate><title>Method and an apparatus to reduce duty cycle distortion</title><author>STIFF JONATHON C ; KWAN KING H</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7170319B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>STIFF JONATHON C</creatorcontrib><creatorcontrib>KWAN KING H</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>STIFF JONATHON C</au><au>KWAN KING H</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and an apparatus to reduce duty cycle distortion</title><date>2007-01-30</date><risdate>2007</risdate><abstract>A method and an apparatus to reduce duty cycle distortion are described. The apparatus may include a first current-mode logic (CML) circuit block comprising a positive input and a negative input and a second CML circuit block coupled in series to the first CML circuit block. The second CML circuit block may comprise a positive output, a negative output and a first transistor coupled between the positive input and the positive output. The second transistor may be coupled between the negative input and the negative output of the second CML circuit block.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US7170319B1
source esp@cenet
subjects AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title Method and an apparatus to reduce duty cycle distortion
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-11T15%3A28%3A09IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=STIFF%20JONATHON%20C&rft.date=2007-01-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7170319B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true