Process and lead frame for making leadless semiconductor packages

A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connec...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: PARK HYUNGJUN, RHO KYUNGSOO, WON JINHEE, PARK SANGBAE, YANG JUNYOUNG, KIM HYEONGNO, LEE YONGGIL
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator PARK HYUNGJUN
RHO KYUNGSOO
WON JINHEE
PARK SANGBAE
YANG JUNYOUNG
KIM HYEONGNO
LEE YONGGIL
description A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7169651B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7169651B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7169651B23</originalsourceid><addsrcrecordid>eNrjZHAMKMpPTi0uVkjMS1HISU1MUUgrSsxNVUjLL1LITczOzEsHi-aAlBSn5mYm5-ellCaXAGULEpOzE9NTi3kYWNMSc4pTeaE0N4OCm2uIs4duakF-fGoxUFlqXmpJfGiwuaGZpZmpoZORMRFKAJoCMXw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Process and lead frame for making leadless semiconductor packages</title><source>esp@cenet</source><creator>PARK HYUNGJUN ; RHO KYUNGSOO ; WON JINHEE ; PARK SANGBAE ; YANG JUNYOUNG ; KIM HYEONGNO ; LEE YONGGIL</creator><creatorcontrib>PARK HYUNGJUN ; RHO KYUNGSOO ; WON JINHEE ; PARK SANGBAE ; YANG JUNYOUNG ; KIM HYEONGNO ; LEE YONGGIL</creatorcontrib><description>A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070130&amp;DB=EPODOC&amp;CC=US&amp;NR=7169651B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070130&amp;DB=EPODOC&amp;CC=US&amp;NR=7169651B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PARK HYUNGJUN</creatorcontrib><creatorcontrib>RHO KYUNGSOO</creatorcontrib><creatorcontrib>WON JINHEE</creatorcontrib><creatorcontrib>PARK SANGBAE</creatorcontrib><creatorcontrib>YANG JUNYOUNG</creatorcontrib><creatorcontrib>KIM HYEONGNO</creatorcontrib><creatorcontrib>LEE YONGGIL</creatorcontrib><title>Process and lead frame for making leadless semiconductor packages</title><description>A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAMKMpPTi0uVkjMS1HISU1MUUgrSsxNVUjLL1LITczOzEsHi-aAlBSn5mYm5-ellCaXAGULEpOzE9NTi3kYWNMSc4pTeaE0N4OCm2uIs4duakF-fGoxUFlqXmpJfGiwuaGZpZmpoZORMRFKAJoCMXw</recordid><startdate>20070130</startdate><enddate>20070130</enddate><creator>PARK HYUNGJUN</creator><creator>RHO KYUNGSOO</creator><creator>WON JINHEE</creator><creator>PARK SANGBAE</creator><creator>YANG JUNYOUNG</creator><creator>KIM HYEONGNO</creator><creator>LEE YONGGIL</creator><scope>EVB</scope></search><sort><creationdate>20070130</creationdate><title>Process and lead frame for making leadless semiconductor packages</title><author>PARK HYUNGJUN ; RHO KYUNGSOO ; WON JINHEE ; PARK SANGBAE ; YANG JUNYOUNG ; KIM HYEONGNO ; LEE YONGGIL</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7169651B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>PARK HYUNGJUN</creatorcontrib><creatorcontrib>RHO KYUNGSOO</creatorcontrib><creatorcontrib>WON JINHEE</creatorcontrib><creatorcontrib>PARK SANGBAE</creatorcontrib><creatorcontrib>YANG JUNYOUNG</creatorcontrib><creatorcontrib>KIM HYEONGNO</creatorcontrib><creatorcontrib>LEE YONGGIL</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PARK HYUNGJUN</au><au>RHO KYUNGSOO</au><au>WON JINHEE</au><au>PARK SANGBAE</au><au>YANG JUNYOUNG</au><au>KIM HYEONGNO</au><au>LEE YONGGIL</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Process and lead frame for making leadless semiconductor packages</title><date>2007-01-30</date><risdate>2007</risdate><abstract>A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US7169651B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Process and lead frame for making leadless semiconductor packages
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T10%3A14%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PARK%20HYUNGJUN&rft.date=2007-01-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7169651B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true