Dual access DRAM
A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additiona...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | PARRIS MICHAEL C BUTLER DOUGLAS BLAINE JONES, JR. OSCAR FREDERICK |
description | A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7110306B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7110306B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7110306B23</originalsourceid><addsrcrecordid>eNrjZBBwKU3MUUhMTk4tLlZwCXL05WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHB5oaGBsYGZk5GxkQoAQAfXh4J</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Dual access DRAM</title><source>esp@cenet</source><creator>PARRIS MICHAEL C ; BUTLER DOUGLAS BLAINE ; JONES, JR. OSCAR FREDERICK</creator><creatorcontrib>PARRIS MICHAEL C ; BUTLER DOUGLAS BLAINE ; JONES, JR. OSCAR FREDERICK</creatorcontrib><description>A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060919&DB=EPODOC&CC=US&NR=7110306B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060919&DB=EPODOC&CC=US&NR=7110306B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PARRIS MICHAEL C</creatorcontrib><creatorcontrib>BUTLER DOUGLAS BLAINE</creatorcontrib><creatorcontrib>JONES, JR. OSCAR FREDERICK</creatorcontrib><title>Dual access DRAM</title><description>A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBBwKU3MUUhMTk4tLlZwCXL05WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHB5oaGBsYGZk5GxkQoAQAfXh4J</recordid><startdate>20060919</startdate><enddate>20060919</enddate><creator>PARRIS MICHAEL C</creator><creator>BUTLER DOUGLAS BLAINE</creator><creator>JONES, JR. OSCAR FREDERICK</creator><scope>EVB</scope></search><sort><creationdate>20060919</creationdate><title>Dual access DRAM</title><author>PARRIS MICHAEL C ; BUTLER DOUGLAS BLAINE ; JONES, JR. OSCAR FREDERICK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7110306B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>PARRIS MICHAEL C</creatorcontrib><creatorcontrib>BUTLER DOUGLAS BLAINE</creatorcontrib><creatorcontrib>JONES, JR. OSCAR FREDERICK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PARRIS MICHAEL C</au><au>BUTLER DOUGLAS BLAINE</au><au>JONES, JR. OSCAR FREDERICK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Dual access DRAM</title><date>2006-09-19</date><risdate>2006</risdate><abstract>A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US7110306B2 |
source | esp@cenet |
subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
title | Dual access DRAM |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-13T13%3A23%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PARRIS%20MICHAEL%20C&rft.date=2006-09-19&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7110306B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |