Integrated circuit package with leadframe enhancement and method of manufacturing the same

An integrated circuit package having a die pad and a plurality of leads is disclosed. At least one of the plurality of leads has a recess formed in a first face thereof. The package also has an integrated circuit chip coupled to the die pad through an adhesive layer. A plurality of wires each link a...

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Hauptverfasser: MANALAC RODEL, SIAT JAIME, TAN HIEN BOON, POH FRANCIS, CORDERO ROLAND
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creator MANALAC RODEL
SIAT JAIME
TAN HIEN BOON
POH FRANCIS
CORDERO ROLAND
description An integrated circuit package having a die pad and a plurality of leads is disclosed. At least one of the plurality of leads has a recess formed in a first face thereof. The package also has an integrated circuit chip coupled to the die pad through an adhesive layer. A plurality of wires each link a first face of the integrated circuit chip to one of the plurality of leads. An encapsulant encloses the integrated circuit chip, the plurality of wires, the die pad, and a portion of each of the plurality of leads. The encapsulant forms a plurality of side walls which slant downward and outward. At least one of the side walls intersects with the first face of the at least one lead within the side walls of the recess formed therein.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7109570B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7109570B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7109570B23</originalsourceid><addsrcrecordid>eNqNjbEKwjAURbs4iPoP7weEqkhxVRSd1cWlPJKbJti8lOQVf98OfoDTWc7hzKvXTRRdZoUlE7IZg9LA5s0d6BPUUw-2LnMEQTyLQYQosViKUJ8sJUeRZXRsdMxBOlIPKlOwrGaO-4LVj4uKLufH6brGkFqU6QKBts97s6kP-6Y-bnd_KF_S6Dr6</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit package with leadframe enhancement and method of manufacturing the same</title><source>esp@cenet</source><creator>MANALAC RODEL ; SIAT JAIME ; TAN HIEN BOON ; POH FRANCIS ; CORDERO ROLAND</creator><creatorcontrib>MANALAC RODEL ; SIAT JAIME ; TAN HIEN BOON ; POH FRANCIS ; CORDERO ROLAND</creatorcontrib><description>An integrated circuit package having a die pad and a plurality of leads is disclosed. At least one of the plurality of leads has a recess formed in a first face thereof. The package also has an integrated circuit chip coupled to the die pad through an adhesive layer. A plurality of wires each link a first face of the integrated circuit chip to one of the plurality of leads. An encapsulant encloses the integrated circuit chip, the plurality of wires, the die pad, and a portion of each of the plurality of leads. The encapsulant forms a plurality of side walls which slant downward and outward. At least one of the side walls intersects with the first face of the at least one lead within the side walls of the recess formed therein.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060919&amp;DB=EPODOC&amp;CC=US&amp;NR=7109570B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060919&amp;DB=EPODOC&amp;CC=US&amp;NR=7109570B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MANALAC RODEL</creatorcontrib><creatorcontrib>SIAT JAIME</creatorcontrib><creatorcontrib>TAN HIEN BOON</creatorcontrib><creatorcontrib>POH FRANCIS</creatorcontrib><creatorcontrib>CORDERO ROLAND</creatorcontrib><title>Integrated circuit package with leadframe enhancement and method of manufacturing the same</title><description>An integrated circuit package having a die pad and a plurality of leads is disclosed. At least one of the plurality of leads has a recess formed in a first face thereof. The package also has an integrated circuit chip coupled to the die pad through an adhesive layer. A plurality of wires each link a first face of the integrated circuit chip to one of the plurality of leads. An encapsulant encloses the integrated circuit chip, the plurality of wires, the die pad, and a portion of each of the plurality of leads. The encapsulant forms a plurality of side walls which slant downward and outward. At least one of the side walls intersects with the first face of the at least one lead within the side walls of the recess formed therein.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjbEKwjAURbs4iPoP7weEqkhxVRSd1cWlPJKbJti8lOQVf98OfoDTWc7hzKvXTRRdZoUlE7IZg9LA5s0d6BPUUw-2LnMEQTyLQYQosViKUJ8sJUeRZXRsdMxBOlIPKlOwrGaO-4LVj4uKLufH6brGkFqU6QKBts97s6kP-6Y-bnd_KF_S6Dr6</recordid><startdate>20060919</startdate><enddate>20060919</enddate><creator>MANALAC RODEL</creator><creator>SIAT JAIME</creator><creator>TAN HIEN BOON</creator><creator>POH FRANCIS</creator><creator>CORDERO ROLAND</creator><scope>EVB</scope></search><sort><creationdate>20060919</creationdate><title>Integrated circuit package with leadframe enhancement and method of manufacturing the same</title><author>MANALAC RODEL ; SIAT JAIME ; TAN HIEN BOON ; POH FRANCIS ; CORDERO ROLAND</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7109570B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MANALAC RODEL</creatorcontrib><creatorcontrib>SIAT JAIME</creatorcontrib><creatorcontrib>TAN HIEN BOON</creatorcontrib><creatorcontrib>POH FRANCIS</creatorcontrib><creatorcontrib>CORDERO ROLAND</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MANALAC RODEL</au><au>SIAT JAIME</au><au>TAN HIEN BOON</au><au>POH FRANCIS</au><au>CORDERO ROLAND</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit package with leadframe enhancement and method of manufacturing the same</title><date>2006-09-19</date><risdate>2006</risdate><abstract>An integrated circuit package having a die pad and a plurality of leads is disclosed. At least one of the plurality of leads has a recess formed in a first face thereof. The package also has an integrated circuit chip coupled to the die pad through an adhesive layer. A plurality of wires each link a first face of the integrated circuit chip to one of the plurality of leads. An encapsulant encloses the integrated circuit chip, the plurality of wires, the die pad, and a portion of each of the plurality of leads. The encapsulant forms a plurality of side walls which slant downward and outward. At least one of the side walls intersects with the first face of the at least one lead within the side walls of the recess formed therein.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Integrated circuit package with leadframe enhancement and method of manufacturing the same
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T20%3A43%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MANALAC%20RODEL&rft.date=2006-09-19&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7109570B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true