Method and apparatus for coordinating dynamic memory deallocation with a redundant bit line steering mechanism

A method and apparatus for coordinating dynamic memory page deallocation with a redundant bit line steering mechanism are provided. With the method and apparatus, memory scrubbing and redundant bit line steering operations are performed in parallel with handling of notifications of runtime correctab...

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Hauptverfasser:	LEMMON WAYNE L, SHANKAR RAVI A, NAYAR NARESH, KITAMORN ALONGKORN, HENDERSON DANIEL JAMES
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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creator	LEMMON WAYNE L SHANKAR RAVI A NAYAR NARESH KITAMORN ALONGKORN HENDERSON DANIEL JAMES
description	A method and apparatus for coordinating dynamic memory page deallocation with a redundant bit line steering mechanism are provided. With the method and apparatus, memory scrubbing and redundant bit line steering operations are performed in parallel with handling of notifications of runtime correctable errors. When a correctable error is encountered during runtime, and the correctable error is determined to be persistent, then dynamic memory page deallocation is requested of a hypervisor. The determination of persistence is based on a history CE table that is populated by the operation of the memory scrubbing and redundant bit line steering mechanism of a service processor. Thus, only those correctable errors that persist for longer than one memory scrubbing cycle are subject to memory page deallocation.
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
title	Method and apparatus for coordinating dynamic memory deallocation with a redundant bit line steering mechanism
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