Method and apparatus for multi-port memory controller

A memory controller is provided. The memory controller includes an initiator block configured to arbitrate requests corresponding to data from multiple ports. The initiator block includes an arbitration module configured to consider a latency factor and a bandwidth factor associated with the data fr...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	BISHOP WENDY, MATTA ASHWIN, SHRADER STEVEN
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY MULTIPLEX COMMUNICATION PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	BISHOP WENDY MATTA ASHWIN SHRADER STEVEN
description	A memory controller is provided. The memory controller includes an initiator block configured to arbitrate requests corresponding to data from multiple ports. The initiator block includes an arbitration module configured to consider a latency factor and a bandwidth factor associated with the data from a port to be selected for processing. A state machine is in communication with the arbitration module. The state machine is configured to generate a signal to the arbitration module that is configured to select the data associated with the port based upon the latency factor and the bandwidth factor. Task status and completion circuitry configured to calculate the bandwidth factor based upon previous data selected from the port is included in the initiator block. The task status and completion circuitry is further configured to transmit the calculated bandwidth factor to the state machine. A method for arbitrating across multiple ports is also provided.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7054968B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7054968B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7054968B23</originalsourceid><addsrcrecordid>eNrjZDD1TS3JyE9RSMwD4oKCxKLEktJihbT8IoXc0pySTN2C_KIShdzU3PyiSoXk_LySovycnNQiHgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oSHxpsbmBqYmlm4WRkTIQSADPWLWI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for multi-port memory controller</title><source>esp@cenet</source><creator>BISHOP WENDY ; MATTA ASHWIN ; SHRADER STEVEN</creator><creatorcontrib>BISHOP WENDY ; MATTA ASHWIN ; SHRADER STEVEN</creatorcontrib><description>A memory controller is provided. The memory controller includes an initiator block configured to arbitrate requests corresponding to data from multiple ports. The initiator block includes an arbitration module configured to consider a latency factor and a bandwidth factor associated with the data from a port to be selected for processing. A state machine is in communication with the arbitration module. The state machine is configured to generate a signal to the arbitration module that is configured to select the data associated with the port based upon the latency factor and the bandwidth factor. Task status and completion circuitry configured to calculate the bandwidth factor based upon previous data selected from the port is included in the initiator block. The task status and completion circuitry is further configured to transmit the calculated bandwidth factor to the state machine. A method for arbitrating across multiple ports is also provided.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; MULTIPLEX COMMUNICATION ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060530&DB=EPODOC&CC=US&NR=7054968B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060530&DB=EPODOC&CC=US&NR=7054968B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BISHOP WENDY</creatorcontrib><creatorcontrib>MATTA ASHWIN</creatorcontrib><creatorcontrib>SHRADER STEVEN</creatorcontrib><title>Method and apparatus for multi-port memory controller</title><description>A memory controller is provided. The memory controller includes an initiator block configured to arbitrate requests corresponding to data from multiple ports. The initiator block includes an arbitration module configured to consider a latency factor and a bandwidth factor associated with the data from a port to be selected for processing. A state machine is in communication with the arbitration module. The state machine is configured to generate a signal to the arbitration module that is configured to select the data associated with the port based upon the latency factor and the bandwidth factor. Task status and completion circuitry configured to calculate the bandwidth factor based upon previous data selected from the port is included in the initiator block. The task status and completion circuitry is further configured to transmit the calculated bandwidth factor to the state machine. A method for arbitrating across multiple ports is also provided.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>MULTIPLEX COMMUNICATION</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD1TS3JyE9RSMwD4oKCxKLEktJihbT8IoXc0pySTN2C_KIShdzU3PyiSoXk_LySovycnNQiHgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oSHxpsbmBqYmlm4WRkTIQSADPWLWI</recordid><startdate>20060530</startdate><enddate>20060530</enddate><creator>BISHOP WENDY</creator><creator>MATTA ASHWIN</creator><creator>SHRADER STEVEN</creator><scope>EVB</scope></search><sort><creationdate>20060530</creationdate><title>Method and apparatus for multi-port memory controller</title><author>BISHOP WENDY ; MATTA ASHWIN ; SHRADER STEVEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7054968B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>MULTIPLEX COMMUNICATION</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>BISHOP WENDY</creatorcontrib><creatorcontrib>MATTA ASHWIN</creatorcontrib><creatorcontrib>SHRADER STEVEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BISHOP WENDY</au><au>MATTA ASHWIN</au><au>SHRADER STEVEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for multi-port memory controller</title><date>2006-05-30</date><risdate>2006</risdate><abstract>A memory controller is provided. The memory controller includes an initiator block configured to arbitrate requests corresponding to data from multiple ports. The initiator block includes an arbitration module configured to consider a latency factor and a bandwidth factor associated with the data from a port to be selected for processing. A state machine is in communication with the arbitration module. The state machine is configured to generate a signal to the arbitration module that is configured to select the data associated with the port based upon the latency factor and the bandwidth factor. Task status and completion circuitry configured to calculate the bandwidth factor based upon previous data selected from the port is included in the initiator block. The task status and completion circuitry is further configured to transmit the calculated bandwidth factor to the state machine. A method for arbitrating across multiple ports is also provided.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US7054968B2
source	esp@cenet
subjects	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY MULTIPLEX COMMUNICATION PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title	Method and apparatus for multi-port memory controller
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T12%3A43%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BISHOP%20WENDY&rft.date=2006-05-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7054968B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true