Multi chip module assembly

A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second int...

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Hauptverfasser: RAJAGOPALAN SARATHY, MCCORMICK JOHN P, ALAGARATNAM MANIAM, DESAI KISHOR
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Sprache:eng
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creator RAJAGOPALAN SARATHY
MCCORMICK JOHN P
ALAGARATNAM MANIAM
DESAI KISHOR
description A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7041516B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7041516B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7041516B23</originalsourceid><addsrcrecordid>eNrjZJDyLc0pyVRIzsgsUMjNTynNSVVILC5OzU3KqeRhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhweYGJoamhmZORsZEKAEABYgiuA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Multi chip module assembly</title><source>esp@cenet</source><creator>RAJAGOPALAN SARATHY ; MCCORMICK JOHN P ; ALAGARATNAM MANIAM ; DESAI KISHOR</creator><creatorcontrib>RAJAGOPALAN SARATHY ; MCCORMICK JOHN P ; ALAGARATNAM MANIAM ; DESAI KISHOR</creatorcontrib><description>A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060509&amp;DB=EPODOC&amp;CC=US&amp;NR=7041516B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060509&amp;DB=EPODOC&amp;CC=US&amp;NR=7041516B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RAJAGOPALAN SARATHY</creatorcontrib><creatorcontrib>MCCORMICK JOHN P</creatorcontrib><creatorcontrib>ALAGARATNAM MANIAM</creatorcontrib><creatorcontrib>DESAI KISHOR</creatorcontrib><title>Multi chip module assembly</title><description>A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJDyLc0pyVRIzsgsUMjNTynNSVVILC5OzU3KqeRhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhweYGJoamhmZORsZEKAEABYgiuA</recordid><startdate>20060509</startdate><enddate>20060509</enddate><creator>RAJAGOPALAN SARATHY</creator><creator>MCCORMICK JOHN P</creator><creator>ALAGARATNAM MANIAM</creator><creator>DESAI KISHOR</creator><scope>EVB</scope></search><sort><creationdate>20060509</creationdate><title>Multi chip module assembly</title><author>RAJAGOPALAN SARATHY ; MCCORMICK JOHN P ; ALAGARATNAM MANIAM ; DESAI KISHOR</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7041516B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>RAJAGOPALAN SARATHY</creatorcontrib><creatorcontrib>MCCORMICK JOHN P</creatorcontrib><creatorcontrib>ALAGARATNAM MANIAM</creatorcontrib><creatorcontrib>DESAI KISHOR</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RAJAGOPALAN SARATHY</au><au>MCCORMICK JOHN P</au><au>ALAGARATNAM MANIAM</au><au>DESAI KISHOR</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Multi chip module assembly</title><date>2006-05-09</date><risdate>2006</risdate><abstract>A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
title Multi chip module assembly
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T02%3A45%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=RAJAGOPALAN%20SARATHY&rft.date=2006-05-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7041516B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true