Host adapter integrated data FIFO and data cache and method for improved host adapter sourcing latency

A host adapter, which interfaces two I/O buses, caches data transferred from one I/O bus to another I/O bus in a data first-in-first-out (FIFO)/caching memory. In addition, when a target device on the another I/O bus is ready to receive the data, data is transferred from the data FIFO/caching memory...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	YOUNG B. ARLEN
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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