Dual word line mode for DRAMs
An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a wo...
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creator | PARRIS MICHAEL C BUTLER DOUGLAS BLAINE JONES, JR. OSCAR FREDERICK |
description | An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a word line sequence when first converting stored data in the array of memory cells from the first operational mode to the second operational mode. The word line sequence includes activating a first word line, developing a valid signal on a corresponding bit line, and then activating a second word line while the first word line is still active. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7002874B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7002874B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7002874B13</originalsourceid><addsrcrecordid>eNrjZJB1KU3MUSjPL0pRyMnMS1XIzU9JVUjLL1JwCXL0LeZhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhweYGBkYW5iZOhsZEKAEAJv4i2Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Dual word line mode for DRAMs</title><source>esp@cenet</source><creator>PARRIS MICHAEL C ; BUTLER DOUGLAS BLAINE ; JONES, JR. OSCAR FREDERICK</creator><creatorcontrib>PARRIS MICHAEL C ; BUTLER DOUGLAS BLAINE ; JONES, JR. OSCAR FREDERICK</creatorcontrib><description>An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a word line sequence when first converting stored data in the array of memory cells from the first operational mode to the second operational mode. The word line sequence includes activating a first word line, developing a valid signal on a corresponding bit line, and then activating a second word line while the first word line is still active.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060221&DB=EPODOC&CC=US&NR=7002874B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060221&DB=EPODOC&CC=US&NR=7002874B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PARRIS MICHAEL C</creatorcontrib><creatorcontrib>BUTLER DOUGLAS BLAINE</creatorcontrib><creatorcontrib>JONES, JR. OSCAR FREDERICK</creatorcontrib><title>Dual word line mode for DRAMs</title><description>An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a word line sequence when first converting stored data in the array of memory cells from the first operational mode to the second operational mode. The word line sequence includes activating a first word line, developing a valid signal on a corresponding bit line, and then activating a second word line while the first word line is still active.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJB1KU3MUSjPL0pRyMnMS1XIzU9JVUjLL1JwCXL0LeZhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhweYGBkYW5iZOhsZEKAEAJv4i2Q</recordid><startdate>20060221</startdate><enddate>20060221</enddate><creator>PARRIS MICHAEL C</creator><creator>BUTLER DOUGLAS BLAINE</creator><creator>JONES, JR. OSCAR FREDERICK</creator><scope>EVB</scope></search><sort><creationdate>20060221</creationdate><title>Dual word line mode for DRAMs</title><author>PARRIS MICHAEL C ; BUTLER DOUGLAS BLAINE ; JONES, JR. OSCAR FREDERICK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7002874B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>PARRIS MICHAEL C</creatorcontrib><creatorcontrib>BUTLER DOUGLAS BLAINE</creatorcontrib><creatorcontrib>JONES, JR. OSCAR FREDERICK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PARRIS MICHAEL C</au><au>BUTLER DOUGLAS BLAINE</au><au>JONES, JR. OSCAR FREDERICK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Dual word line mode for DRAMs</title><date>2006-02-21</date><risdate>2006</risdate><abstract>An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a word line sequence when first converting stored data in the array of memory cells from the first operational mode to the second operational mode. The word line sequence includes activating a first word line, developing a valid signal on a corresponding bit line, and then activating a second word line while the first word line is still active.</abstract><oa>free_for_read</oa></addata></record> |
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title | Dual word line mode for DRAMs |
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