Dual word line mode for DRAMs

An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a wo...

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Hauptverfasser: PARRIS MICHAEL C, BUTLER DOUGLAS BLAINE, JONES, JR. OSCAR FREDERICK
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creator PARRIS MICHAEL C
BUTLER DOUGLAS BLAINE
JONES, JR. OSCAR FREDERICK
description An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a word line sequence when first converting stored data in the array of memory cells from the first operational mode to the second operational mode. The word line sequence includes activating a first word line, developing a valid signal on a corresponding bit line, and then activating a second word line while the first word line is still active.
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STATIC STORES
title Dual word line mode for DRAMs
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