Self-aligned isolation double-gate FET

A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. First...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	CHAN KEVIN K, ROY RONNEN A, IEONG MEIKEI, YANG MIN, COHEN GUY M, SOLOMON PAUL
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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