Latency time circuit for an S-DRAM
Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control...
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| creator | KIESER SABINE DIETRICH STEFAN SCHROEGMEIER PETER ACHARYA PRAMOD |
| description | Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, characterized by at least one comparison circuit, which compares the cycle time of the high-frequency clock signal with a predetermined decoding time and by a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time. |
| format | Patent |
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| subjects | AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES |
| title | Latency time circuit for an S-DRAM |
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