Redundant array architecture for word replacement in CAM

Redundant array architecture for word replacement in CAM

The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translati...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: BUSCH ROBERT E, KOCH GARY S, WISTORT REID A, TOWLER FRED J, BATSON KEVIN A
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator BUSCH ROBERT E
KOCH GARY S
WISTORT REID A
TOWLER FRED J
BATSON KEVIN A
description The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6791855B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6791855B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6791855B23</originalsourceid><addsrcrecordid>eNrjZLAISk0pzUtJzCtRSCwqSqwEkskZmSWpySWlRakKaflFCuX5RSkKRakFOYnJqbmpQHWZeQrOjr48DKxpiTnFqbxQmptBwc01xNlDN7UgPz61uACoOi-1JD402Mzc0tDC1NTJyJgIJQCqOS3l</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Redundant array architecture for word replacement in CAM</title><source>esp@cenet</source><creator>BUSCH ROBERT E ; KOCH GARY S ; WISTORT REID A ; TOWLER FRED J ; BATSON KEVIN A</creator><creatorcontrib>BUSCH ROBERT E ; KOCH GARY S ; WISTORT REID A ; TOWLER FRED J ; BATSON KEVIN A</creatorcontrib><description>The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.</description><edition>7</edition><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040914&amp;DB=EPODOC&amp;CC=US&amp;NR=6791855B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040914&amp;DB=EPODOC&amp;CC=US&amp;NR=6791855B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BUSCH ROBERT E</creatorcontrib><creatorcontrib>KOCH GARY S</creatorcontrib><creatorcontrib>WISTORT REID A</creatorcontrib><creatorcontrib>TOWLER FRED J</creatorcontrib><creatorcontrib>BATSON KEVIN A</creatorcontrib><title>Redundant array architecture for word replacement in CAM</title><description>The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAISk0pzUtJzCtRSCwqSqwEkskZmSWpySWlRakKaflFCuX5RSkKRakFOYnJqbmpQHWZeQrOjr48DKxpiTnFqbxQmptBwc01xNlDN7UgPz61uACoOi-1JD402Mzc0tDC1NTJyJgIJQCqOS3l</recordid><startdate>20040914</startdate><enddate>20040914</enddate><creator>BUSCH ROBERT E</creator><creator>KOCH GARY S</creator><creator>WISTORT REID A</creator><creator>TOWLER FRED J</creator><creator>BATSON KEVIN A</creator><scope>EVB</scope></search><sort><creationdate>20040914</creationdate><title>Redundant array architecture for word replacement in CAM</title><author>BUSCH ROBERT E ; KOCH GARY S ; WISTORT REID A ; TOWLER FRED J ; BATSON KEVIN A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6791855B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>BUSCH ROBERT E</creatorcontrib><creatorcontrib>KOCH GARY S</creatorcontrib><creatorcontrib>WISTORT REID A</creatorcontrib><creatorcontrib>TOWLER FRED J</creatorcontrib><creatorcontrib>BATSON KEVIN A</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BUSCH ROBERT E</au><au>KOCH GARY S</au><au>WISTORT REID A</au><au>TOWLER FRED J</au><au>BATSON KEVIN A</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Redundant array architecture for word replacement in CAM</title><date>2004-09-14</date><risdate>2004</risdate><abstract>The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US6791855B2
source esp@cenet
subjects INFORMATION STORAGE
PHYSICS
STATIC STORES
title Redundant array architecture for word replacement in CAM
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T08%3A25%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BUSCH%20ROBERT%20E&rft.date=2004-09-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS6791855B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true