Synchronization of vertical retrace for multiple participating graphics computers
A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buff...
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| creator | SARCAR KANOJ TORNES JAMES MUKHERJEE SHRIJEET |
| description | A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6791551B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6791551B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6791551B23</originalsourceid><addsrcrecordid>eNqNjDEKwkAQAK-xEPUP-wGLKFFsFcVWonVYjr1k4XK37G0Efb0RfIDVFDPM3N2aV_K95sRvNM4JcoAnqbHHCEqm6AlCVhjGaCyRQPBrWaY8ddApSs--gM-DjEZalm4WMBZa_bhwcDnfT9c1SW6pyDRMZO2j2e0PVV1Xx832j-QDErg4yg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Synchronization of vertical retrace for multiple participating graphics computers</title><source>esp@cenet</source><creator>SARCAR KANOJ ; TORNES JAMES ; MUKHERJEE SHRIJEET</creator><creatorcontrib>SARCAR KANOJ ; TORNES JAMES ; MUKHERJEE SHRIJEET</creatorcontrib><description>A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.</description><edition>7</edition><language>eng</language><subject>ADVERTISING ; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION ; CALCULATING ; COMPUTING ; COUNTING ; CRYPTOGRAPHY ; DISPLAY ; EDUCATION ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS ; SEALS</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040914&DB=EPODOC&CC=US&NR=6791551B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040914&DB=EPODOC&CC=US&NR=6791551B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SARCAR KANOJ</creatorcontrib><creatorcontrib>TORNES JAMES</creatorcontrib><creatorcontrib>MUKHERJEE SHRIJEET</creatorcontrib><title>Synchronization of vertical retrace for multiple participating graphics computers</title><description>A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.</description><subject>ADVERTISING</subject><subject>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>CRYPTOGRAPHY</subject><subject>DISPLAY</subject><subject>EDUCATION</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><subject>SEALS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjDEKwkAQAK-xEPUP-wGLKFFsFcVWonVYjr1k4XK37G0Efb0RfIDVFDPM3N2aV_K95sRvNM4JcoAnqbHHCEqm6AlCVhjGaCyRQPBrWaY8ddApSs--gM-DjEZalm4WMBZa_bhwcDnfT9c1SW6pyDRMZO2j2e0PVV1Xx832j-QDErg4yg</recordid><startdate>20040914</startdate><enddate>20040914</enddate><creator>SARCAR KANOJ</creator><creator>TORNES JAMES</creator><creator>MUKHERJEE SHRIJEET</creator><scope>EVB</scope></search><sort><creationdate>20040914</creationdate><title>Synchronization of vertical retrace for multiple participating graphics computers</title><author>SARCAR KANOJ ; TORNES JAMES ; MUKHERJEE SHRIJEET</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6791551B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>ADVERTISING</topic><topic>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>CRYPTOGRAPHY</topic><topic>DISPLAY</topic><topic>EDUCATION</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><topic>SEALS</topic><toplevel>online_resources</toplevel><creatorcontrib>SARCAR KANOJ</creatorcontrib><creatorcontrib>TORNES JAMES</creatorcontrib><creatorcontrib>MUKHERJEE SHRIJEET</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SARCAR KANOJ</au><au>TORNES JAMES</au><au>MUKHERJEE SHRIJEET</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Synchronization of vertical retrace for multiple participating graphics computers</title><date>2004-09-14</date><risdate>2004</risdate><abstract>A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CALCULATING COMPUTING COUNTING CRYPTOGRAPHY DISPLAY EDUCATION ELECTRIC DIGITAL DATA PROCESSING PHYSICS SEALS |
| title | Synchronization of vertical retrace for multiple participating graphics computers |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-07T05%3A56%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SARCAR%20KANOJ&rft.date=2004-09-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS6791551B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |