Semiconductor memory device with efficiently laid-out internal interconnection lines

In a dummy word line region, a second metal interconnection line is arranged, and a connection between a low-resistive metal interconnection line constituting a word line arranged in a normal word line region and a lower gate electrode line is shifted. In a bit line twisting region, a memory cell ga...

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Hauptverfasser:	AMANO TERUHIKO, YANO KENJI
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES
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creator	AMANO TERUHIKO YANO KENJI
description	In a dummy word line region, a second metal interconnection line is arranged, and a connection between a low-resistive metal interconnection line constituting a word line arranged in a normal word line region and a lower gate electrode line is shifted. In a bit line twisting region, a memory cell gate electrode line is arranged to interconnect the gates of access transistors of memory cells, and a twisted bit line structure is implemented utilizing an upper metal interconnection line. A memory cell array region can more efficiently be used.
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title	Semiconductor memory device with efficiently laid-out internal interconnection lines
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