Method and apparatus for removing digital glitches

A method and apparatus for removing glitches, interference or noise from a clock signal are provided by the present invention. In accordance with the invention, a glitch-ridden clock signal is monitored to determine when a transition in the glitch ridden clock signal occurs. When a transition occurs...

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Hauptverfasser: MCMAHAN DENNIS B, MORGAN JASON N, ROCHELL TIMOTHY D
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creator MCMAHAN DENNIS B
MORGAN JASON N
ROCHELL TIMOTHY D
description A method and apparatus for removing glitches, interference or noise from a clock signal are provided by the present invention. In accordance with the invention, a glitch-ridden clock signal is monitored to determine when a transition in the glitch ridden clock signal occurs. When a transition occurs, a counter is initiated in accordance with a second high-speed clock signal. The value of this counter is compared to a compare value. The compare value is selected to approximately equal the expected period of the glitch-ridden clock signal. If the counter value equals the compare value, it is assumed that the transition was a valid transition and the transition is carried through and output as a glitch-free clock signal. However, if a transition occurs before the count value equals the counter compare value, it is assumed that the transition is invalid and no transition is carried to the glitch-free clock output. Thus, the present invention removes glitches from a received clock signal and outputs a glitch-free clock signal.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6728649B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6728649B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6728649B23</originalsourceid><addsrcrecordid>eNrjZDDyTS3JyE9RSMwD4oKCxKLEktJihbT8IoWi1Nz8ssy8dIWUzPTMksQchfSczJLkjNRiHgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oSHxpsZm5kYWZi6WRkTIQSAH8KLAM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for removing digital glitches</title><source>esp@cenet</source><creator>MCMAHAN DENNIS B ; MORGAN JASON N ; ROCHELL TIMOTHY D</creator><creatorcontrib>MCMAHAN DENNIS B ; MORGAN JASON N ; ROCHELL TIMOTHY D</creatorcontrib><description>A method and apparatus for removing glitches, interference or noise from a clock signal are provided by the present invention. In accordance with the invention, a glitch-ridden clock signal is monitored to determine when a transition in the glitch ridden clock signal occurs. When a transition occurs, a counter is initiated in accordance with a second high-speed clock signal. The value of this counter is compared to a compare value. The compare value is selected to approximately equal the expected period of the glitch-ridden clock signal. If the counter value equals the compare value, it is assumed that the transition was a valid transition and the transition is carried through and output as a glitch-free clock signal. However, if a transition occurs before the count value equals the counter compare value, it is assumed that the transition is invalid and no transition is carried to the glitch-free clock output. Thus, the present invention removes glitches from a received clock signal and outputs a glitch-free clock signal.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040427&amp;DB=EPODOC&amp;CC=US&amp;NR=6728649B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040427&amp;DB=EPODOC&amp;CC=US&amp;NR=6728649B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MCMAHAN DENNIS B</creatorcontrib><creatorcontrib>MORGAN JASON N</creatorcontrib><creatorcontrib>ROCHELL TIMOTHY D</creatorcontrib><title>Method and apparatus for removing digital glitches</title><description>A method and apparatus for removing glitches, interference or noise from a clock signal are provided by the present invention. In accordance with the invention, a glitch-ridden clock signal is monitored to determine when a transition in the glitch ridden clock signal occurs. When a transition occurs, a counter is initiated in accordance with a second high-speed clock signal. The value of this counter is compared to a compare value. The compare value is selected to approximately equal the expected period of the glitch-ridden clock signal. If the counter value equals the compare value, it is assumed that the transition was a valid transition and the transition is carried through and output as a glitch-free clock signal. However, if a transition occurs before the count value equals the counter compare value, it is assumed that the transition is invalid and no transition is carried to the glitch-free clock output. Thus, the present invention removes glitches from a received clock signal and outputs a glitch-free clock signal.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDyTS3JyE9RSMwD4oKCxKLEktJihbT8IoWi1Nz8ssy8dIWUzPTMksQchfSczJLkjNRiHgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oSHxpsZm5kYWZi6WRkTIQSAH8KLAM</recordid><startdate>20040427</startdate><enddate>20040427</enddate><creator>MCMAHAN DENNIS B</creator><creator>MORGAN JASON N</creator><creator>ROCHELL TIMOTHY D</creator><scope>EVB</scope></search><sort><creationdate>20040427</creationdate><title>Method and apparatus for removing digital glitches</title><author>MCMAHAN DENNIS B ; MORGAN JASON N ; ROCHELL TIMOTHY D</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6728649B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>MCMAHAN DENNIS B</creatorcontrib><creatorcontrib>MORGAN JASON N</creatorcontrib><creatorcontrib>ROCHELL TIMOTHY D</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MCMAHAN DENNIS B</au><au>MORGAN JASON N</au><au>ROCHELL TIMOTHY D</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for removing digital glitches</title><date>2004-04-27</date><risdate>2004</risdate><abstract>A method and apparatus for removing glitches, interference or noise from a clock signal are provided by the present invention. In accordance with the invention, a glitch-ridden clock signal is monitored to determine when a transition in the glitch ridden clock signal occurs. When a transition occurs, a counter is initiated in accordance with a second high-speed clock signal. The value of this counter is compared to a compare value. The compare value is selected to approximately equal the expected period of the glitch-ridden clock signal. If the counter value equals the compare value, it is assumed that the transition was a valid transition and the transition is carried through and output as a glitch-free clock signal. However, if a transition occurs before the count value equals the counter compare value, it is assumed that the transition is invalid and no transition is carried to the glitch-free clock output. Thus, the present invention removes glitches from a received clock signal and outputs a glitch-free clock signal.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title Method and apparatus for removing digital glitches
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T06%3A17%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MCMAHAN%20DENNIS%20B&rft.date=2004-04-27&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS6728649B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true