Dual die memory

A double-sized chip assembly and method is provided for two back-to-back integrated-circuit chips which both have the same fabrication mask sets. An electrically-selectable bonding-pad connection option alternatively provides a standard, non-reversed, option NRO for a bonding-pad layout and a non-st...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	CALLAHAN JOHN M
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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