Method for the reduction of lateral shrinkage in multilayer circuit boards on a substrate
A method of controlling shrinkage in aligned green tape stacks during firing comprises providing a topmost layer of a ceramic material having a sintering temperature higher than that of the ceramic used to make the green tapes and firing above the sintering temperature of the green tape ceramic but...
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| creator | THALER BARRY JAY PRABHU ASHOK NARAYAN KUMAR ANANDA HOSAKERE |
| description | A method of controlling shrinkage in aligned green tape stacks during firing comprises providing a topmost layer of a ceramic material having a sintering temperature higher than that of the ceramic used to make the green tapes and firing above the sintering temperature of the green tape ceramic but below the sintering temperature of the topmost layer ceramic. The method of the invention provides improved shrinkage control for green tape stacks on a support substrate. |
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The method of the invention provides improved shrinkage control for green tape stacks on a support substrate.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC ; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS ; LAYERED PRODUCTS ; LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM ; PERFORMING OPERATIONS ; SEMICONDUCTOR DEVICES ; TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ; TECHNICAL SUBJECTS COVERED BY FORMER USPC ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ; TRANSPORTING</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040323&DB=EPODOC&CC=US&NR=6709749B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040323&DB=EPODOC&CC=US&NR=6709749B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>THALER BARRY JAY</creatorcontrib><creatorcontrib>PRABHU ASHOK NARAYAN</creatorcontrib><creatorcontrib>KUMAR ANANDA HOSAKERE</creatorcontrib><title>Method for the reduction of lateral shrinkage in multilayer circuit boards on a substrate</title><description>A method of controlling shrinkage in aligned green tape stacks during firing comprises providing a topmost layer of a ceramic material having a sintering temperature higher than that of the ceramic used to make the green tapes and firing above the sintering temperature of the green tape ceramic but below the sintering temperature of the topmost layer ceramic. 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The method of the invention provides improved shrinkage control for green tape stacks on a support substrate.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS LAYERED PRODUCTS LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM PERFORMING OPERATIONS SEMICONDUCTOR DEVICES TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TRANSPORTING |
| title | Method for the reduction of lateral shrinkage in multilayer circuit boards on a substrate |
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