Data structure for fine-grid multi-level VLSI routing and method for storing the data structure in a computer readable medium

Data structure for fine-grid multi-level VLSI routing and method for storing the data structure in a computer readable medium

Provided is a data structure containing wiring information for an integrated circuit and a method for storing the same in a computer readable medium. In one embodiment of the present invention storage of the data structure is achieved by mapping said integrated circuit into memory locations of said...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MEHROTRA SHARAD, PATEL PARSOTAM T
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator MEHROTRA SHARAD
PATEL PARSOTAM T
description Provided is a data structure containing wiring information for an integrated circuit and a method for storing the same in a computer readable medium. In one embodiment of the present invention storage of the data structure is achieved by mapping said integrated circuit into memory locations of said medium as a wiring plane having a plurality of data points arranged in a grid. Each of the plurality of data points having state information associated therewith, which includes a plurality of attributes. Subsections of the grid are associated with memory locations in the computer readable medium to form a plurality of tiles. Specifically the tiles and data points are arranged so that a sub-portion of the data points associated with one of the plurality of tiles have common attributes.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6694502B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6694502B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6694502B23</originalsourceid><addsrcrecordid>eNqNjL0KwkAQhNNYiPoO-wIBiRqw9Q8Fu6htWHN7ycHl7tjbs_PdjWJjZzUw830zzp47FIQonBpJTKA9gzaO8paNgj5ZMbmlB1m4nasTsE9iXAvohpGk8-pjRPH8rqUjUL-HxgFC4_uQhBiYUOHd0iArk_ppNtJoI82-OcngsL9sjzkFX1MM2JAjqa9VWa6Xq3mxKRZ_IC9so0d4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Data structure for fine-grid multi-level VLSI routing and method for storing the data structure in a computer readable medium</title><source>esp@cenet</source><creator>MEHROTRA SHARAD ; PATEL PARSOTAM T</creator><creatorcontrib>MEHROTRA SHARAD ; PATEL PARSOTAM T</creatorcontrib><description>Provided is a data structure containing wiring information for an integrated circuit and a method for storing the same in a computer readable medium. In one embodiment of the present invention storage of the data structure is achieved by mapping said integrated circuit into memory locations of said medium as a wiring plane having a plurality of data points arranged in a grid. Each of the plurality of data points having state information associated therewith, which includes a plurality of attributes. Subsections of the grid are associated with memory locations in the computer readable medium to form a plurality of tiles. Specifically the tiles and data points are arranged so that a sub-portion of the data points associated with one of the plurality of tiles have common attributes.</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040217&amp;DB=EPODOC&amp;CC=US&amp;NR=6694502B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040217&amp;DB=EPODOC&amp;CC=US&amp;NR=6694502B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MEHROTRA SHARAD</creatorcontrib><creatorcontrib>PATEL PARSOTAM T</creatorcontrib><title>Data structure for fine-grid multi-level VLSI routing and method for storing the data structure in a computer readable medium</title><description>Provided is a data structure containing wiring information for an integrated circuit and a method for storing the same in a computer readable medium. In one embodiment of the present invention storage of the data structure is achieved by mapping said integrated circuit into memory locations of said medium as a wiring plane having a plurality of data points arranged in a grid. Each of the plurality of data points having state information associated therewith, which includes a plurality of attributes. Subsections of the grid are associated with memory locations in the computer readable medium to form a plurality of tiles. Specifically the tiles and data points are arranged so that a sub-portion of the data points associated with one of the plurality of tiles have common attributes.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjL0KwkAQhNNYiPoO-wIBiRqw9Q8Fu6htWHN7ycHl7tjbs_PdjWJjZzUw830zzp47FIQonBpJTKA9gzaO8paNgj5ZMbmlB1m4nasTsE9iXAvohpGk8-pjRPH8rqUjUL-HxgFC4_uQhBiYUOHd0iArk_ppNtJoI82-OcngsL9sjzkFX1MM2JAjqa9VWa6Xq3mxKRZ_IC9so0d4</recordid><startdate>20040217</startdate><enddate>20040217</enddate><creator>MEHROTRA SHARAD</creator><creator>PATEL PARSOTAM T</creator><scope>EVB</scope></search><sort><creationdate>20040217</creationdate><title>Data structure for fine-grid multi-level VLSI routing and method for storing the data structure in a computer readable medium</title><author>MEHROTRA SHARAD ; PATEL PARSOTAM T</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6694502B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>MEHROTRA SHARAD</creatorcontrib><creatorcontrib>PATEL PARSOTAM T</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MEHROTRA SHARAD</au><au>PATEL PARSOTAM T</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Data structure for fine-grid multi-level VLSI routing and method for storing the data structure in a computer readable medium</title><date>2004-02-17</date><risdate>2004</risdate><abstract>Provided is a data structure containing wiring information for an integrated circuit and a method for storing the same in a computer readable medium. In one embodiment of the present invention storage of the data structure is achieved by mapping said integrated circuit into memory locations of said medium as a wiring plane having a plurality of data points arranged in a grid. Each of the plurality of data points having state information associated therewith, which includes a plurality of attributes. Subsections of the grid are associated with memory locations in the computer readable medium to form a plurality of tiles. Specifically the tiles and data points are arranged so that a sub-portion of the data points associated with one of the plurality of tiles have common attributes.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US6694502B2
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Data structure for fine-grid multi-level VLSI routing and method for storing the data structure in a computer readable medium
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T18%3A55%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MEHROTRA%20SHARAD&rft.date=2004-02-17&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS6694502B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true