Method for forming crack resistant planarizing layer within microelectronic fabrication
Within a method for forming a planarizing layer within a microelectronic fabrication, there is employed formed upon a partially photoexposed planarizing layer formed of a partially photoexposed negative photoresist material a sacrificial layer. Within the method, when sequentially: (1) stripping fro...
Gespeichert in:
| Hauptverfasser: | , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | WONG FU-TIEN CHANG CHIH-KUNG KUO CHIN CHEN HSIUNG CHUNG SHENG HSIAO YU-KUNG PAN SHENG LIANG |
| description | Within a method for forming a planarizing layer within a microelectronic fabrication, there is employed formed upon a partially photoexposed planarizing layer formed of a partially photoexposed negative photoresist material a sacrificial layer. Within the method, when sequentially: (1) stripping from the partially photoexposed planarizing layer the sacrificial layer; and (2) developing the partially photoexposed planarizing layer to form a developed planarizing layer, the developed planarizing layer is formed with enhanced planarity and diminished thickness. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6660641B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6660641B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6660641B13</originalsourceid><addsrcrecordid>eNqNikEKwkAMAHvxIOof8gHBouwDlIoXTyoeS4ypDW6zSzYg-nop-AAPwxxmptX1yN6nO3TJRgbRB5AhPcG4SHFUhxxR0eQztohvNniJ96IwCFniyOSWVAg6vJkQuiSdV5MOY-HFz7MK9s15d1hyTi2XjMTK3l5OIYRV2NTbev3H8gVjYTq2</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for forming crack resistant planarizing layer within microelectronic fabrication</title><source>esp@cenet</source><creator>WONG FU-TIEN ; CHANG CHIH-KUNG ; KUO CHIN CHEN ; HSIUNG CHUNG SHENG ; HSIAO YU-KUNG ; PAN SHENG LIANG</creator><creatorcontrib>WONG FU-TIEN ; CHANG CHIH-KUNG ; KUO CHIN CHEN ; HSIUNG CHUNG SHENG ; HSIAO YU-KUNG ; PAN SHENG LIANG</creatorcontrib><description>Within a method for forming a planarizing layer within a microelectronic fabrication, there is employed formed upon a partially photoexposed planarizing layer formed of a partially photoexposed negative photoresist material a sacrificial layer. Within the method, when sequentially: (1) stripping from the partially photoexposed planarizing layer the sacrificial layer; and (2) developing the partially photoexposed planarizing layer to form a developed planarizing layer, the developed planarizing layer is formed with enhanced planarity and diminished thickness.</description><edition>7</edition><language>eng</language><subject>APPARATUS SPECIALLY ADAPTED THEREFOR ; BASIC ELECTRIC ELEMENTS ; CINEMATOGRAPHY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; ELECTROGRAPHY ; HOLOGRAPHY ; MATERIALS THEREFOR ; ORIGINALS THEREFOR ; PHOTOGRAPHY ; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20031209&DB=EPODOC&CC=US&NR=6660641B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20031209&DB=EPODOC&CC=US&NR=6660641B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WONG FU-TIEN</creatorcontrib><creatorcontrib>CHANG CHIH-KUNG</creatorcontrib><creatorcontrib>KUO CHIN CHEN</creatorcontrib><creatorcontrib>HSIUNG CHUNG SHENG</creatorcontrib><creatorcontrib>HSIAO YU-KUNG</creatorcontrib><creatorcontrib>PAN SHENG LIANG</creatorcontrib><title>Method for forming crack resistant planarizing layer within microelectronic fabrication</title><description>Within a method for forming a planarizing layer within a microelectronic fabrication, there is employed formed upon a partially photoexposed planarizing layer formed of a partially photoexposed negative photoresist material a sacrificial layer. Within the method, when sequentially: (1) stripping from the partially photoexposed planarizing layer the sacrificial layer; and (2) developing the partially photoexposed planarizing layer to form a developed planarizing layer, the developed planarizing layer is formed with enhanced planarity and diminished thickness.</description><subject>APPARATUS SPECIALLY ADAPTED THEREFOR</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CINEMATOGRAPHY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>ELECTROGRAPHY</subject><subject>HOLOGRAPHY</subject><subject>MATERIALS THEREFOR</subject><subject>ORIGINALS THEREFOR</subject><subject>PHOTOGRAPHY</subject><subject>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNikEKwkAMAHvxIOof8gHBouwDlIoXTyoeS4ypDW6zSzYg-nop-AAPwxxmptX1yN6nO3TJRgbRB5AhPcG4SHFUhxxR0eQztohvNniJ96IwCFniyOSWVAg6vJkQuiSdV5MOY-HFz7MK9s15d1hyTi2XjMTK3l5OIYRV2NTbev3H8gVjYTq2</recordid><startdate>20031209</startdate><enddate>20031209</enddate><creator>WONG FU-TIEN</creator><creator>CHANG CHIH-KUNG</creator><creator>KUO CHIN CHEN</creator><creator>HSIUNG CHUNG SHENG</creator><creator>HSIAO YU-KUNG</creator><creator>PAN SHENG LIANG</creator><scope>EVB</scope></search><sort><creationdate>20031209</creationdate><title>Method for forming crack resistant planarizing layer within microelectronic fabrication</title><author>WONG FU-TIEN ; CHANG CHIH-KUNG ; KUO CHIN CHEN ; HSIUNG CHUNG SHENG ; HSIAO YU-KUNG ; PAN SHENG LIANG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6660641B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><topic>APPARATUS SPECIALLY ADAPTED THEREFOR</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CINEMATOGRAPHY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>ELECTROGRAPHY</topic><topic>HOLOGRAPHY</topic><topic>MATERIALS THEREFOR</topic><topic>ORIGINALS THEREFOR</topic><topic>PHOTOGRAPHY</topic><topic>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>WONG FU-TIEN</creatorcontrib><creatorcontrib>CHANG CHIH-KUNG</creatorcontrib><creatorcontrib>KUO CHIN CHEN</creatorcontrib><creatorcontrib>HSIUNG CHUNG SHENG</creatorcontrib><creatorcontrib>HSIAO YU-KUNG</creatorcontrib><creatorcontrib>PAN SHENG LIANG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WONG FU-TIEN</au><au>CHANG CHIH-KUNG</au><au>KUO CHIN CHEN</au><au>HSIUNG CHUNG SHENG</au><au>HSIAO YU-KUNG</au><au>PAN SHENG LIANG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for forming crack resistant planarizing layer within microelectronic fabrication</title><date>2003-12-09</date><risdate>2003</risdate><abstract>Within a method for forming a planarizing layer within a microelectronic fabrication, there is employed formed upon a partially photoexposed planarizing layer formed of a partially photoexposed negative photoresist material a sacrificial layer. Within the method, when sequentially: (1) stripping from the partially photoexposed planarizing layer the sacrificial layer; and (2) developing the partially photoexposed planarizing layer to form a developed planarizing layer, the developed planarizing layer is formed with enhanced planarity and diminished thickness.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US6660641B1 |
| source | esp@cenet |
| subjects | APPARATUS SPECIALLY ADAPTED THEREFOR BASIC ELECTRIC ELEMENTS CINEMATOGRAPHY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROGRAPHY HOLOGRAPHY MATERIALS THEREFOR ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS SEMICONDUCTOR DEVICES |
| title | Method for forming crack resistant planarizing layer within microelectronic fabrication |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-10T05%3A14%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=WONG%20FU-TIEN&rft.date=2003-12-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS6660641B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |