Integrated circuit package employing flip-chip technology and method of assembly
An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | ALLEN GREG L HARPER TIMOTHY V |
| description | An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6659512B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6659512B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6659512B13</originalsourceid><addsrcrecordid>eNqNzD0OwjAMQOEsDAi4gy_QoaBWYqUCwYYEzJVJnB-RxFFjht4eBg7A9JZPb6mulyzkJhQyoMOk30GgoH6hI6BUIs8hO7AxlEb7UEBI-8yR3QyYDSQSzwbYAtZK6RnntVpYjJU2v64UnI734dxQ4ZHq902ZZHzc-r7bd-320O7-IB9aqjdm</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit package employing flip-chip technology and method of assembly</title><source>esp@cenet</source><creator>ALLEN GREG L ; HARPER TIMOTHY V</creator><creatorcontrib>ALLEN GREG L ; HARPER TIMOTHY V</creatorcontrib><description>An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20031209&DB=EPODOC&CC=US&NR=6659512B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20031209&DB=EPODOC&CC=US&NR=6659512B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ALLEN GREG L</creatorcontrib><creatorcontrib>HARPER TIMOTHY V</creatorcontrib><title>Integrated circuit package employing flip-chip technology and method of assembly</title><description>An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzD0OwjAMQOEsDAi4gy_QoaBWYqUCwYYEzJVJnB-RxFFjht4eBg7A9JZPb6mulyzkJhQyoMOk30GgoH6hI6BUIs8hO7AxlEb7UEBI-8yR3QyYDSQSzwbYAtZK6RnntVpYjJU2v64UnI734dxQ4ZHq902ZZHzc-r7bd-320O7-IB9aqjdm</recordid><startdate>20031209</startdate><enddate>20031209</enddate><creator>ALLEN GREG L</creator><creator>HARPER TIMOTHY V</creator><scope>EVB</scope></search><sort><creationdate>20031209</creationdate><title>Integrated circuit package employing flip-chip technology and method of assembly</title><author>ALLEN GREG L ; HARPER TIMOTHY V</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6659512B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ALLEN GREG L</creatorcontrib><creatorcontrib>HARPER TIMOTHY V</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ALLEN GREG L</au><au>HARPER TIMOTHY V</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit package employing flip-chip technology and method of assembly</title><date>2003-12-09</date><risdate>2003</risdate><abstract>An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US6659512B1 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
| title | Integrated circuit package employing flip-chip technology and method of assembly |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T06%3A50%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ALLEN%20GREG%20L&rft.date=2003-12-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS6659512B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |