Semiconductor package device
Disclosed are semiconductor packages and methods incorporating the use of vias in layers of leaded and nonleaded multilayer packages. The vias provide fluid communication between layers such that bonding material flows among layers for the formation of a 3D bond. As disclosed, the layers may compris...
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creator | COLLIER TERENCE QUINTIN |
description | Disclosed are semiconductor packages and methods incorporating the use of vias in layers of leaded and nonleaded multilayer packages. The vias provide fluid communication between layers such that bonding material flows among layers for the formation of a 3D bond. As disclosed, the layers may comprise leads, dice, bond pads, or other substantially planar semiconductor package surfaces. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6646332B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6646332B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6646332B23</originalsourceid><addsrcrecordid>eNrjZJAJTs3NTM7PSylNLskvUihITM5OTE9VSEkty0xO5WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcVAxal5qSXxocFmZiZmxsZGTkbGRCgBAHEWI6w</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor package device</title><source>esp@cenet</source><creator>COLLIER TERENCE QUINTIN</creator><creatorcontrib>COLLIER TERENCE QUINTIN</creatorcontrib><description>Disclosed are semiconductor packages and methods incorporating the use of vias in layers of leaded and nonleaded multilayer packages. The vias provide fluid communication between layers such that bonding material flows among layers for the formation of a 3D bond. As disclosed, the layers may comprise leads, dice, bond pads, or other substantially planar semiconductor package surfaces.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC ; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE</subject><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20031111&DB=EPODOC&CC=US&NR=6646332B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20031111&DB=EPODOC&CC=US&NR=6646332B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>COLLIER TERENCE QUINTIN</creatorcontrib><title>Semiconductor package device</title><description>Disclosed are semiconductor packages and methods incorporating the use of vias in layers of leaded and nonleaded multilayer packages. The vias provide fluid communication between layers such that bonding material flows among layers for the formation of a 3D bond. As disclosed, the layers may comprise leads, dice, bond pads, or other substantially planar semiconductor package surfaces.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</subject><subject>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><subject>TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAJTs3NTM7PSylNLskvUihITM5OTE9VSEkty0xO5WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcVAxal5qSXxocFmZiZmxsZGTkbGRCgBAHEWI6w</recordid><startdate>20031111</startdate><enddate>20031111</enddate><creator>COLLIER TERENCE QUINTIN</creator><scope>EVB</scope></search><sort><creationdate>20031111</creationdate><title>Semiconductor package device</title><author>COLLIER TERENCE QUINTIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6646332B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</topic><topic>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</topic><topic>TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE</topic><toplevel>online_resources</toplevel><creatorcontrib>COLLIER TERENCE QUINTIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>COLLIER TERENCE QUINTIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor package device</title><date>2003-11-11</date><risdate>2003</risdate><abstract>Disclosed are semiconductor packages and methods incorporating the use of vias in layers of leaded and nonleaded multilayer packages. The vias provide fluid communication between layers such that bonding material flows among layers for the formation of a 3D bond. As disclosed, the layers may comprise leads, dice, bond pads, or other substantially planar semiconductor package surfaces.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE |
title | Semiconductor package device |
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