System and method for maintaining lock of a phase locked loop feedback during clock halt

A system and method for maintaining lock of a phase locked loop within an integrated circuit during both a normal operation mode and a test mode, and during switching from the normal operation mode to the test mode, is disclosed. The method includes closing a phase locked loop feedback path of the p...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	HELDER EDWARD R
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS PULSE TECHNIQUE TESTING
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