Method and an apparatus for synthesizing a programmable logic circuit

A method for describing a user programmable logic function generator in a Hardware Description Language (HDL), e.g., Verilog is disclosed. The logic function generator includes a multiplexer having a plurality of select inputs and a plurality of programmable data inputs. The logic function generator...

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Bibliographische Detailangaben

1. Verfasser:	HAUCK LANE
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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