Precision digital delay element having stable operation over varied manufacturing processes and environmental operating conditions

A digital delay circuit employs a stable reference clock signal, delayed by a reference delay line, to obtain information related to delay characteristics of a matching input delay line. An input clock signal is delayed by the input delay line, which provides a plurality of variously delayed input clock signals based upon the input clock signal. The reference delay line provides a plurality of variously delayed reference clock signals based upon the stable reference clock signal; the delayed reference clock signals convey information related to the operating characteristics of both delay lines. In response to such information, one of the delayed input clock signals can be selected as a delayed clock output. The reference and input delay lines are configured such that the delay circuit consistently generates a delayed clock output having an actual delay that falls within a specified range of delay.