Loop cache memory and cache controller for pipelined microprocessors

A microprocessor and method for operating this microprocessor are disclosed. The microprocessor contains multiple execution units that receive instructions from an instruction pipeline. A loop cache memory is connected in communication with the instruction pipeline, such that it may both store instr...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	SCALES RICHARD H
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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