Linear vector computation
A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The processing engine includes a coefficient register 940 for holding a representation of each of N coefficients of a first input vector. A test unit...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | DJAFARIAN KARIM CLAVE GAEL LAURENTI GILBERT |
| description | A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The processing engine includes a coefficient register 940 for holding a representation of each of N coefficients of a first input vector. A test unit 950 is provided for testing selected parts (e.g. bits) of the coefficient register for respective coefficient representations. An arithmetic unit 970 computes respective coordinates of an output vector by selective addition/subtraction of coordinates of a second input vector dependent on results of the coefficient representation tests. Power consumption can be kept low due to the use of a coefficient test operation in parallel with an ALU operation. Each coordinate of an output vector {right arrow over (Y can be computed with a N+1 step algorithm, the computation being done with bit test unit operating in parallel with an ALU according to the following equation:At a step (i+1)1 |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6557097B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6557097B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6557097B13</originalsourceid><addsrcrecordid>eNrjZJD0ycxLTSxSKEtNLskvUkjOzy0oLUksyczP42FgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBZqam5gaW5k6GxkQoAQD54SK_</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Linear vector computation</title><source>esp@cenet</source><creator>DJAFARIAN KARIM ; CLAVE GAEL ; LAURENTI GILBERT</creator><creatorcontrib>DJAFARIAN KARIM ; CLAVE GAEL ; LAURENTI GILBERT</creatorcontrib><description>A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The processing engine includes a coefficient register 940 for holding a representation of each of N coefficients of a first input vector. A test unit 950 is provided for testing selected parts (e.g. bits) of the coefficient register for respective coefficient representations. An arithmetic unit 970 computes respective coordinates of an output vector by selective addition/subtraction of coordinates of a second input vector dependent on results of the coefficient representation tests. Power consumption can be kept low due to the use of a coefficient test operation in parallel with an ALU operation. Each coordinate of an output vector {right arrow over (Y can be computed with a N+1 step algorithm, the computation being done with bit test unit operating in parallel with an ALU according to the following equation:At a step (i+1)1<=i<=N of the computation, a bit Ci+1 of the CPU register is addressed, this bit is tested in a temporary register and a conditional addition/subtraction of a coordinate of the second input vector Xij is performed.</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TELEPHONIC COMMUNICATION</subject><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20030429&DB=EPODOC&CC=US&NR=6557097B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20030429&DB=EPODOC&CC=US&NR=6557097B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DJAFARIAN KARIM</creatorcontrib><creatorcontrib>CLAVE GAEL</creatorcontrib><creatorcontrib>LAURENTI GILBERT</creatorcontrib><title>Linear vector computation</title><description>A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The processing engine includes a coefficient register 940 for holding a representation of each of N coefficients of a first input vector. A test unit 950 is provided for testing selected parts (e.g. bits) of the coefficient register for respective coefficient representations. An arithmetic unit 970 computes respective coordinates of an output vector by selective addition/subtraction of coordinates of a second input vector dependent on results of the coefficient representation tests. Power consumption can be kept low due to the use of a coefficient test operation in parallel with an ALU operation. Each coordinate of an output vector {right arrow over (Y can be computed with a N+1 step algorithm, the computation being done with bit test unit operating in parallel with an ALU according to the following equation:At a step (i+1)1<=i<=N of the computation, a bit Ci+1 of the CPU register is addressed, this bit is tested in a temporary register and a conditional addition/subtraction of a coordinate of the second input vector Xij is performed.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TELEPHONIC COMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJD0ycxLTSxSKEtNLskvUkjOzy0oLUksyczP42FgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBZqam5gaW5k6GxkQoAQD54SK_</recordid><startdate>20030429</startdate><enddate>20030429</enddate><creator>DJAFARIAN KARIM</creator><creator>CLAVE GAEL</creator><creator>LAURENTI GILBERT</creator><scope>EVB</scope></search><sort><creationdate>20030429</creationdate><title>Linear vector computation</title><author>DJAFARIAN KARIM ; CLAVE GAEL ; LAURENTI GILBERT</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6557097B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TELEPHONIC COMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>DJAFARIAN KARIM</creatorcontrib><creatorcontrib>CLAVE GAEL</creatorcontrib><creatorcontrib>LAURENTI GILBERT</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DJAFARIAN KARIM</au><au>CLAVE GAEL</au><au>LAURENTI GILBERT</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Linear vector computation</title><date>2003-04-29</date><risdate>2003</risdate><abstract>A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The processing engine includes a coefficient register 940 for holding a representation of each of N coefficients of a first input vector. A test unit 950 is provided for testing selected parts (e.g. bits) of the coefficient register for respective coefficient representations. An arithmetic unit 970 computes respective coordinates of an output vector by selective addition/subtraction of coordinates of a second input vector dependent on results of the coefficient representation tests. Power consumption can be kept low due to the use of a coefficient test operation in parallel with an ALU operation. Each coordinate of an output vector {right arrow over (Y can be computed with a N+1 step algorithm, the computation being done with bit test unit operating in parallel with an ALU according to the following equation:At a step (i+1)1<=i<=N of the computation, a bit Ci+1 of the CPU register is addressed, this bit is tested in a temporary register and a conditional addition/subtraction of a coordinate of the second input vector Xij is performed.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US6557097B1 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TELEPHONIC COMMUNICATION |
| title | Linear vector computation |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-12T13%3A08%3A07IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=DJAFARIAN%20KARIM&rft.date=2003-04-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS6557097B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |