Clocking scheme for ASIC

A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of t...

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Hauptverfasser:	PRATT SUSAN M, O'REILLY PADRAIC, CREEDON TADHG, LARDNER MIKE, HUGHES SUZANNE M, GAVIN VINCENT
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	PRATT SUSAN M O'REILLY PADRAIC CREEDON TADHG LARDNER MIKE HUGHES SUZANNE M GAVIN VINCENT
description	A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronizers.
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	Clocking scheme for ASIC
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