Random access memory with divided memory banks and data read/write architecture therefor

A dynamic random access memory with two divided memory banks is disclosed wherein memory cells are divided into first and second groups each of which includes an array of memory cells connected to a corresponding word line. Those memory cells are sub-divided into subgroups each of which has four mem...

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description A dynamic random access memory with two divided memory banks is disclosed wherein memory cells are divided into first and second groups each of which includes an array of memory cells connected to a corresponding word line. Those memory cells are sub-divided into subgroups each of which has four memory cells. A first set of input/output lines is provided for the first group of memory cells, and a second set of input/output lines is provided for the second group of memory cells. An output circuit section is connected to the those sets of input/output lines to output data transferred thereto. An access controller section specifies subgroups alternately from the first and second groups of memory cells with four memory cells as a substantial access minimum unit, accesses memory cells of a specified subgroup to read stored data therefrom and transfers the read data to corresponding input/output lines associated therewith. The read data is supplied to the output circuit section for conversion to serial data and then output therefrom.
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title Random access memory with divided memory banks and data read/write architecture therefor
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