Flash EEPROM with integrated device for limiting the erase source voltage

A flash EEPROM having an array of memory cells which include a common source line connecting together source electrodes of the memory cells. A resistive feedback element is coupled in series between the common source line and a positive potential when the memory cells must be electrically erased. Th...

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Bibliographische Detailangaben

Hauptverfasser:	FRATIN LORENZO, RIVA CARLO, RAVAZZI LEONARDO
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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