Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit

Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as...

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Hauptverfasser:	EMER JOEL S, EDWARDS BRUCE E, STAMM REBECCA L, HICKS, JR. JAMES E, FOSSUM TRYGGVE, REILLY MATTHEW H, ZILLES CRAIG B, JOERG CHRISTOPHER F
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	EMER JOEL S EDWARDS BRUCE E STAMM REBECCA L HICKS, JR. JAMES E FOSSUM TRYGGVE REILLY MATTHEW H ZILLES CRAIG B JOERG CHRISTOPHER F
description	Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit
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