Integrated NAND and flip-flop circuit
A combination NAND and flip-flop circuit includes a pre-NAND scan circuit operable to receive a plurality of input signals and produce first and second output signals for receipt by a NAND gate. The plurality of signals comprises signals indicative of a first data signal, a second data signal, a sca...
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| creator | HILL ANTHONY M |
| description | A combination NAND and flip-flop circuit includes a pre-NAND scan circuit operable to receive a plurality of input signals and produce first and second output signals for receipt by a NAND gate. The plurality of signals comprises signals indicative of a first data signal, a second data signal, a scan-in signal, and a scan-enable signal. These circuits include a NAND gate having first and second inputs operable to receive the first and second output signals of the pre-NAND scan circuit. They also include a first transmission gate and a first inverter. The transmission gate receives the output of the NAND gate and the inverter receives the output of the transmission gate. The pre-NAND scan circuit is operable to produce the first and second output signals based on the plurality of input signals such that the first and second output signals are defined as described below. When the scan-enable signal is equal to a logical one then the first output signal and the second output signal are either both equal to the scan-in signal or the first output signal is equal to a logical one and the second output signal is equal to the scan-in signal. When the scan-enable signal is equal to a logical zero, then the first output signal is equal to the first data signal and the second output signal is equal to the second data signal. |
| format | Patent |
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The plurality of signals comprises signals indicative of a first data signal, a second data signal, a scan-in signal, and a scan-enable signal. These circuits include a NAND gate having first and second inputs operable to receive the first and second output signals of the pre-NAND scan circuit. They also include a first transmission gate and a first inverter. The transmission gate receives the output of the NAND gate and the inverter receives the output of the transmission gate. The pre-NAND scan circuit is operable to produce the first and second output signals based on the plurality of input signals such that the first and second output signals are defined as described below. When the scan-enable signal is equal to a logical one then the first output signal and the second output signal are either both equal to the scan-in signal or the first output signal is equal to a logical one and the second output signal is equal to the scan-in signal. When the scan-enable signal is equal to a logical zero, then the first output signal is equal to the first data signal and the second output signal is equal to the second data signal.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021210&DB=EPODOC&CC=US&NR=6492841B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021210&DB=EPODOC&CC=US&NR=6492841B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HILL ANTHONY M</creatorcontrib><title>Integrated NAND and flip-flop circuit</title><description>A combination NAND and flip-flop circuit includes a pre-NAND scan circuit operable to receive a plurality of input signals and produce first and second output signals for receipt by a NAND gate. The plurality of signals comprises signals indicative of a first data signal, a second data signal, a scan-in signal, and a scan-enable signal. These circuits include a NAND gate having first and second inputs operable to receive the first and second output signals of the pre-NAND scan circuit. They also include a first transmission gate and a first inverter. The transmission gate receives the output of the NAND gate and the inverter receives the output of the transmission gate. The pre-NAND scan circuit is operable to produce the first and second output signals based on the plurality of input signals such that the first and second output signals are defined as described below. When the scan-enable signal is equal to a logical one then the first output signal and the second output signal are either both equal to the scan-in signal or the first output signal is equal to a logical one and the second output signal is equal to the scan-in signal. When the scan-enable signal is equal to a logical zero, then the first output signal is equal to the first data signal and the second output signal is equal to the second data signal.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD1zCtJTS9KLElNUfBz9HNRSMxLUUjLySzQTcvJL1BIzixKLs0s4WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHBZiaWRhYmhk5GxkQoAQCm6iY5</recordid><startdate>20021210</startdate><enddate>20021210</enddate><creator>HILL ANTHONY M</creator><scope>EVB</scope></search><sort><creationdate>20021210</creationdate><title>Integrated NAND and flip-flop circuit</title><author>HILL ANTHONY M</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6492841B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>HILL ANTHONY M</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HILL ANTHONY M</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated NAND and flip-flop circuit</title><date>2002-12-10</date><risdate>2002</risdate><abstract>A combination NAND and flip-flop circuit includes a pre-NAND scan circuit operable to receive a plurality of input signals and produce first and second output signals for receipt by a NAND gate. The plurality of signals comprises signals indicative of a first data signal, a second data signal, a scan-in signal, and a scan-enable signal. These circuits include a NAND gate having first and second inputs operable to receive the first and second output signals of the pre-NAND scan circuit. They also include a first transmission gate and a first inverter. The transmission gate receives the output of the NAND gate and the inverter receives the output of the transmission gate. The pre-NAND scan circuit is operable to produce the first and second output signals based on the plurality of input signals such that the first and second output signals are defined as described below. When the scan-enable signal is equal to a logical one then the first output signal and the second output signal are either both equal to the scan-in signal or the first output signal is equal to a logical one and the second output signal is equal to the scan-in signal. When the scan-enable signal is equal to a logical zero, then the first output signal is equal to the first data signal and the second output signal is equal to the second data signal.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
| title | Integrated NAND and flip-flop circuit |
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