Ionizing dose hardness assurance technique for CMOS integrated circuits
A method for testing IC devices for radiation hardness in a non-destructive manner, comprising subjecting a device under test (DUT) originally in an insensitized state, to a state in which the DUT is more sensitive to adverse effects of ionizing dose radiation and while the DUT is in the more sensit...
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| creator | LEADON ROLAND E SPRATT JAMES P |
| description | A method for testing IC devices for radiation hardness in a non-destructive manner, comprising subjecting a device under test (DUT) originally in an insensitized state, to a state in which the DUT is more sensitive to adverse effects of ionizing dose radiation and while the DUT is in the more sensitive state, subjecting the DUT to a low level of ionizing radiation to degrade performance of the DUT and electrical testing followed by a restoration of the DUT to its original insensitized state. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6476597B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6476597B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6476597B13</originalsourceid><addsrcrecordid>eNqNyj0OwjAMBtAsDAi4gy_AgIBWrK34GxBDYa6s9GtrCTklThZOz8IBmN7y5u58DSof0YG6YKCRY6cwIzbLkdWDEvyo8s6gPkSqb_eGRBOGyAkdeYk-S7Klm_X8Mqx-Lhydjo_6ssYUWtjEHorUPptiVxb7Q1lttn-ULx1fM_E</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Ionizing dose hardness assurance technique for CMOS integrated circuits</title><source>esp@cenet</source><creator>LEADON ROLAND E ; SPRATT JAMES P</creator><creatorcontrib>LEADON ROLAND E ; SPRATT JAMES P</creatorcontrib><description>A method for testing IC devices for radiation hardness in a non-destructive manner, comprising subjecting a device under test (DUT) originally in an insensitized state, to a state in which the DUT is more sensitive to adverse effects of ionizing dose radiation and while the DUT is in the more sensitive state, subjecting the DUT to a low level of ionizing radiation to degrade performance of the DUT and electrical testing followed by a restoration of the DUT to its original insensitized state.</description><edition>7</edition><language>eng</language><subject>MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021105&DB=EPODOC&CC=US&NR=6476597B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25551,76302</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021105&DB=EPODOC&CC=US&NR=6476597B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEADON ROLAND E</creatorcontrib><creatorcontrib>SPRATT JAMES P</creatorcontrib><title>Ionizing dose hardness assurance technique for CMOS integrated circuits</title><description>A method for testing IC devices for radiation hardness in a non-destructive manner, comprising subjecting a device under test (DUT) originally in an insensitized state, to a state in which the DUT is more sensitive to adverse effects of ionizing dose radiation and while the DUT is in the more sensitive state, subjecting the DUT to a low level of ionizing radiation to degrade performance of the DUT and electrical testing followed by a restoration of the DUT to its original insensitized state.</description><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyj0OwjAMBtAsDAi4gy_AgIBWrK34GxBDYa6s9GtrCTklThZOz8IBmN7y5u58DSof0YG6YKCRY6cwIzbLkdWDEvyo8s6gPkSqb_eGRBOGyAkdeYk-S7Klm_X8Mqx-Lhydjo_6ssYUWtjEHorUPptiVxb7Q1lttn-ULx1fM_E</recordid><startdate>20021105</startdate><enddate>20021105</enddate><creator>LEADON ROLAND E</creator><creator>SPRATT JAMES P</creator><scope>EVB</scope></search><sort><creationdate>20021105</creationdate><title>Ionizing dose hardness assurance technique for CMOS integrated circuits</title><author>LEADON ROLAND E ; SPRATT JAMES P</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6476597B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>LEADON ROLAND E</creatorcontrib><creatorcontrib>SPRATT JAMES P</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEADON ROLAND E</au><au>SPRATT JAMES P</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Ionizing dose hardness assurance technique for CMOS integrated circuits</title><date>2002-11-05</date><risdate>2002</risdate><abstract>A method for testing IC devices for radiation hardness in a non-destructive manner, comprising subjecting a device under test (DUT) originally in an insensitized state, to a state in which the DUT is more sensitive to adverse effects of ionizing dose radiation and while the DUT is in the more sensitive state, subjecting the DUT to a low level of ionizing radiation to degrade performance of the DUT and electrical testing followed by a restoration of the DUT to its original insensitized state.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING |
| title | Ionizing dose hardness assurance technique for CMOS integrated circuits |
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