Electrically adjustable pulse delay circuit

A voltage ramp/threshold variable pulse delay circuit implemented on an IC varies the R instead of the C, which may be fixed. A variable R is formed by a plurality of FET's arranged in parallel. The FET's are sized according to a weighting scheme, which may be binary, and the amount of R produced is determined by which combination of FET's is switched ON, rather than by analog variations in their drive level. If the plurality of sized parallel FET's is made up of individual FET's all of the same polarity, then an undesirable reduction in voltage comparison range will obtain, which may produce an objectionable reduction in available pulse delay if VDD is reduced such that it is no longer many times larger than FET threshold voltage. That reduction in voltage comparison range can be eliminated by replacing each such individual FET with a pair of similarly sized FET's in parallel, the members of which pair are of opposite polarities. The additional FET's have their own drive signals that correspond to the original drive signals.