Method of encapsulated copper (Cu) interconnect formation

A method of forming a semiconductor device having selectively fabricated copper interconnect structure that is encapsulated within selectively formed metallic barriers. An exemplary encapsulated copper interconnect structure includes a first low dielectric constant layer (low K1) formed over a substantially completed semiconductor device on which a first sidewall metallic barrier, consisting of metallic material is formed to line the wall structure of a via. The metallic liner encapsulates a first, substantially thin (>0.25 mum) copper interconnect trench structure is formed overlying and integral with the first copper interconnect structure. A second metallic barrier is deposited over the second selectively formed copper interconnect structure and is formed integral with the first sidewall metallic barrier. The fully encapsulated copper interconnect structure can be further processed to spin coat a second low dielectric constant material layer (low K2) formed about it using the same dielectric material that was used for the low K1 layer. The low K2 layer may be further lithographically processed to form a via structure to provide further electrical interconnect means. The present method facilitates the use of low dielectric material which results in a semiconductor structure that is free of Si3N4 or SiO2 in the copper interconnect region and which overcomes undesirable copper diffusion.