Low hold time statisized dynamic flip-flop
A low hold time flip-flop that has a dynamic input stage and a static output stage is provided. The flip-flop uses a feedback stage to maintain a value on a dynamic node during an evaluation phase of the flip-flop so that an input to the flip-flop only has to be held for a relatively short period of...
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| Format: | Patent |
| Sprache: | eng |
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