Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed

A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step a...

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Hauptverfasser: GIGNAC LYNNE MARIE, WAGNER TINA, ENG CHUNG-PING, LAVOIE CHRISTIAN, PETERSON KIRK DAVID, O'NEIL PATRICIA, WANG YUN-YU, CABRAL, JR. CYRIL, WONG KEITH
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creator GIGNAC LYNNE MARIE
WAGNER TINA
ENG CHUNG-PING
LAVOIE CHRISTIAN
PETERSON KIRK DAVID
O'NEIL PATRICIA
WANG YUN-YU
CABRAL, JR. CYRIL
WONG KEITH
description A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti-Si-Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US6436823B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US6436823B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US6436823B13</originalsourceid><addsrcrecordid>eNqNTDsKAjEQ3cZC1DvMBSw0slgrio02rvUyJBMdSDIxyRbe3ixsYWnxeF_evHlfqbzEgJU0wnN4AkLHN3D4oQQSoEgEsTX1VNBBZseaDU0DDrXJ5FlLMIMu9SeXVMWQCDCYHzf-k1k2M4su02riRQPnU3e8rClKTzmipkClf9zbnWr3W3XYqD8mX4VhQtA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed</title><source>esp@cenet</source><creator>GIGNAC LYNNE MARIE ; WAGNER TINA ; ENG CHUNG-PING ; LAVOIE CHRISTIAN ; PETERSON KIRK DAVID ; O'NEIL PATRICIA ; WANG YUN-YU ; CABRAL, JR. CYRIL ; WONG KEITH</creator><creatorcontrib>GIGNAC LYNNE MARIE ; WAGNER TINA ; ENG CHUNG-PING ; LAVOIE CHRISTIAN ; PETERSON KIRK DAVID ; O'NEIL PATRICIA ; WANG YUN-YU ; CABRAL, JR. CYRIL ; WONG KEITH</creatorcontrib><description>A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti-Si-Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20020820&amp;DB=EPODOC&amp;CC=US&amp;NR=6436823B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20020820&amp;DB=EPODOC&amp;CC=US&amp;NR=6436823B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GIGNAC LYNNE MARIE</creatorcontrib><creatorcontrib>WAGNER TINA</creatorcontrib><creatorcontrib>ENG CHUNG-PING</creatorcontrib><creatorcontrib>LAVOIE CHRISTIAN</creatorcontrib><creatorcontrib>PETERSON KIRK DAVID</creatorcontrib><creatorcontrib>O'NEIL PATRICIA</creatorcontrib><creatorcontrib>WANG YUN-YU</creatorcontrib><creatorcontrib>CABRAL, JR. CYRIL</creatorcontrib><creatorcontrib>WONG KEITH</creatorcontrib><title>Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed</title><description>A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti-Si-Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNTDsKAjEQ3cZC1DvMBSw0slgrio02rvUyJBMdSDIxyRbe3ixsYWnxeF_evHlfqbzEgJU0wnN4AkLHN3D4oQQSoEgEsTX1VNBBZseaDU0DDrXJ5FlLMIMu9SeXVMWQCDCYHzf-k1k2M4su02riRQPnU3e8rClKTzmipkClf9zbnWr3W3XYqD8mX4VhQtA</recordid><startdate>20020820</startdate><enddate>20020820</enddate><creator>GIGNAC LYNNE MARIE</creator><creator>WAGNER TINA</creator><creator>ENG CHUNG-PING</creator><creator>LAVOIE CHRISTIAN</creator><creator>PETERSON KIRK DAVID</creator><creator>O'NEIL PATRICIA</creator><creator>WANG YUN-YU</creator><creator>CABRAL, JR. CYRIL</creator><creator>WONG KEITH</creator><scope>EVB</scope></search><sort><creationdate>20020820</creationdate><title>Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed</title><author>GIGNAC LYNNE MARIE ; WAGNER TINA ; ENG CHUNG-PING ; LAVOIE CHRISTIAN ; PETERSON KIRK DAVID ; O'NEIL PATRICIA ; WANG YUN-YU ; CABRAL, JR. CYRIL ; WONG KEITH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6436823B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>GIGNAC LYNNE MARIE</creatorcontrib><creatorcontrib>WAGNER TINA</creatorcontrib><creatorcontrib>ENG CHUNG-PING</creatorcontrib><creatorcontrib>LAVOIE CHRISTIAN</creatorcontrib><creatorcontrib>PETERSON KIRK DAVID</creatorcontrib><creatorcontrib>O'NEIL PATRICIA</creatorcontrib><creatorcontrib>WANG YUN-YU</creatorcontrib><creatorcontrib>CABRAL, JR. CYRIL</creatorcontrib><creatorcontrib>WONG KEITH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GIGNAC LYNNE MARIE</au><au>WAGNER TINA</au><au>ENG CHUNG-PING</au><au>LAVOIE CHRISTIAN</au><au>PETERSON KIRK DAVID</au><au>O'NEIL PATRICIA</au><au>WANG YUN-YU</au><au>CABRAL, JR. CYRIL</au><au>WONG KEITH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed</title><date>2002-08-20</date><risdate>2002</risdate><abstract>A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti-Si-Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T01%3A41%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=GIGNAC%20LYNNE%20MARIE&rft.date=2002-08-20&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS6436823B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true